Structure and method for integrating MRAM and logic devices

A structure having a memory device region and a logic device region, the structure comprising:

• a first metal layer extending across an interface between the memory device region and the logic device region;
• a dielectric barrier layer over the first metal layer in both the memory device region and the logic device region;
• a first dielectric layer over the dielectric barrier layer in the memory device region;
• magnetic tunneling junction (MTJ) stacks over the first dielectric layer in the memory device region;
• dielectric spacers extending along sidewalls of the MTJ stacks;
• a second dielectric layer over the first dielectric layer and between the dielectric spacers in the memory device region, wherein the second dielectric layer includes a silicon nitride based dielectric material;
• MTJ vias connecting the MTJ stacks to the first metal layer, the MTJ vias isolated from each other by the first dielectric layer;
• an extreme low-k dielectric layer over the dielectric barrier layer in the logic device region and physically contacting sidewalls of the first and second dielectric layers;
• and
• a conductive feature in the logic device region, penetrating the extreme low-k dielectric layer and the dielectric barrier layer, and electrically connecting to the first metal layer.

A structure having a memory device region and a logic device region, the structure comprising:

• a first metal layer extending across an interface between the memory device region and the logic device region;
• a dielectric barrier layer over the first metal layer in both the memory device region and the logic device region;
• a low-k dielectric layer over the dielectric barrier layer in the memory device region and not in the logic device region;
• multiple magnetic tunneling junction (MTJ) devices in the memory device region and not in the logic device region, each of the MTJ devices having an MTJ stack sandwiched between a top and a bottom electrode, wherein the MTJ devices are disposed over the first metal layer, the dielectric barrier layer, and the low-k dielectric layer;
• multiple MTJ vias penetrating through the low-k dielectric layer and the dielectric barrier layer to connect the MTJ devices to the first metal layer;
• a silicon nitride layer over the low-k dielectric layer in the memory device region and not in the logic device region, the silicon nitride layer surrounding the multiple MTJ devices;
• an extreme low-k dielectric layer over the dielectric barrier layer in the logic device region, wherein a portion of the extreme low-k dielectric layer is directly on a top surface of the silicon nitride layer;
• and
• a conductive feature in the logic device region, penetrating the extreme low-k dielectric layer and the dielectric barrier layer, and electrically connecting to the first metal layer.