Memory device and semiconductor device

A semiconductor device, comprising:

• a first transistor;
• a second transistor;
• and
• a capacitor element,
• wherein the first transistor comprises a first oxide semiconductor layer between a first conductive layer and a second conductive layer,
• wherein the first oxide semiconductor layer overlaps with the first conductive layer,
• wherein the second conductive layer overlaps with the first oxide semiconductor layer,
• wherein each of a third conductive layer and a fourth conductive layer is over and in contact with the first oxide semiconductor layer,
• wherein the second conductive layer is electrically connected to one of a source electrode and a drain electrode of the second transistor through a contact hole,
• wherein the third conductive layer comprises a first region which overlaps with the first oxide semiconductor layer and a second region which does not overlap with the first oxide semiconductor layer,
• wherein the second conductive layer comprises a third region which overlaps with the second region of the third conductive layer,
• wherein the third region of the second conductive layer is configured to be a first electrode of the capacitor element,
• wherein the second region of the third conductive layer is configured to be a second electrode of the capacitor element,
• wherein the fourth conductive layer comprises a fourth region,
• wherein the fourth region of the fourth conductive layer and the first conductive layer do not overlap with each other,
• wherein the fourth region of the fourth conductive layer and the second conductive layer do not overlap with each other, and
• wherein a maximum area of the second region of the third conductive layer is larger than a maximum area of the first region of the third conductive layer in a top view.

A semiconductor device, comprising:

• a first transistor;
• a second transistor;
• and
• a capacitor element,
• wherein the first transistor comprises a first oxide semiconductor layer between a first conductive layer and a second conductive layer,
• wherein the second transistor comprises a second oxide semiconductor layer,
• wherein the first oxide semiconductor layer and the first conductive layer overlap with each other,
• wherein the first oxide semiconductor layer and the second conductive layer overlap with each other,
• wherein the second conductive layer is electrically connected to one of a source electrode and a drain electrode of the second transistor,
• wherein a third conductive layer is configured to be one of a source electrode and a drain electrode of the first transistor,
• wherein the third conductive layer comprises a first region which overlaps with the first oxide semiconductor layer and a second region which does not overlap with the first oxide semiconductor layer,
• wherein the second conductive layer comprises a third region which overlaps with the second region of the third conductive layer,
• wherein the third region of the second conductive layer is configured to be a first electrode of the capacitor element, wherein the second region of the third conductive layer is configured to be a second electrode of the capacitor element, and
• wherein a maximum area of the second region of the third conductive layer is larger than a maximum area of the first region of the third conductive layer in a top view.