Multi-level magnetic tunnel junction nor device with wrap-around gate electrodes and methods for forming the same

A method of forming a magnetic tunnel junction memory device, comprising:

• forming a vertical stack comprising at least one instance of a unit layer stack that includes a semiconductor material layer, a metallic material layer, a magnetic tunnel junction layer, and a dielectric spacer layer;
• patterning each instance of the semiconductor material layer in the vertical stack into a plurality of semiconductor channels that are suspended between a semiconductor source region and a semiconductor drain region;
• replacing a portion of each instance of the dielectric spacer layer with a respective instance of a metallic bit line;
• and
• dividing a region of each instance of a combination of the magnetic tunnel junction layer and the metallic material layer within the vertical stack into multiple magnetic tunnel junction memory cells.

A method of forming a magnetic tunnel junction memory device, the method comprising:

• providing a layer stack including a semiconductor material layer, a metallic material layer, a magnetic tunnel junction layer,
• and a dielectric spacer layer;
• patterning the semiconductor material layer into a contiguous structure including a semiconductor source region, a plurality of semiconductor channels, and a plurality of semiconductor drain regions;
• and
• patterning the metallic material layer and the magnetic tunnel junction layer, wherein patterned portions of the magnetic tunnel junction layer comprise a plurality of magnetic tunnel junction memory cells, and patterned portions of the metallic material layer comprise first electrodes underlying a respective one of the plurality of magnetic tunnel junction memory cells, wherein each of the first electrodes is formed on a respective one of the plurality of semiconductor drain regions.