3D ferroelectric memory

A memory device, comprising:

• memory cells in an array disposed in a metal interconnect structure, wherein the memory cells comprise source sides, drain sides, channels extending between the source sides and the drain sides, control gates, and data storage structures between the control gates and the channels;
• an array of vertical stacks comprising conductive strips separated by dielectric strips, wherein the conductive strips extend horizontally to provide a plurality of the control gates;
• a bit line extending vertically, wherein the bit line connects with a plurality of the drain sides;
• and
• a source line extending vertically, wherein the source line connects with a plurality of the source sides;
• wherein the array comprises a vertically repeating arrangement of memory cells, whereby the array comprises vertically adjacent memory cells;
• the data storage structures are provided by data storage films, which are films having a composition, and the data storage films of the vertically adjacent memory cells are discontinuous;
• the dielectric strips have a first width, and the vertical stacks have the first width;
• the conductive strips have a second width which is less than the first width, wherein the second width being less than the first width causes there to be recesses in the vertical stacks at elevations corresponding to the conductive strips;
• and
• the channels are at least partially within the recesses.

A memory device, comprising:

• a memory cell in a three-dimensional array, the memory cell comprising a source side, a drain side, a channel extending between the source side and the drain side, a control gate, and a data storage film between the control gate and the channel;
• a horizontal conductive layer that provides a plurality of the control gates;
• a bit line that extends vertically and connect with a plurality of the drain sides;
• a source line that extends vertically and connects with a plurality of the source sides;
• and
• an upper dielectric layer that is immediately above the horizontal conductive layer;
• and
• a lower dielectric layer that is immediately below the horizontal conductive layer;
• wherein the data storage film has a height that is less than or equal to a thickness of the horizontal conductive layer;
• the upper dielectric layer and the lower dielectric layer extend horizontally beyond the horizontal conductive layer to define a recess for which the upper dielectric layer provides an upper boundary, the lower dielectric layer provides a lower boundary, and the horizontal conductive layer provides a side boundary;
• and
• at least a portion of the channel is within the recess.