Semiconductor memory device and method for manufacturing the same

A method for manufacturing a semiconductor memory device, comprising:

• forming a first dielectric stack region and a second dielectric stack region separated from each other in a first direction;
• forming an array of repeating units which includes a first sub-array of the repeating units and a second sub-array of the repeating units respectively penetrating the first dielectric stack region and the second dielectric stack region, each of the repeating units including a first conductive pillar and a second conductive pillar which are spaced apart from each other by an isolation pillar in a second direction transverse to the first direction, and which extend upwardly in a third direction transverse to the first direction and the second direction, each of the first conductive pillars of the first sub-array being electrically connected to a corresponding one of the first conductive pillars of the second sub-array, and each of the second conductive pillars of the first sub-array being electrically connected to a corresponding one of the second conductive pillars of the second sub-array;
• partially etching the first conductive pillars of the repeating units in the first sub-array and the second conductive pillars of the repeating units in the second sub-array;
• forming a plurality of insulating portions on the etched first conductive pillars and the etched second conductive pillars, respectively;
• partially etching the insulating portions to form a plurality of isolators on the etched first conductive pillars and the etched second conductive pillars, respectively;
• and
• forming a plurality of first conductive portions and a plurality of second conductive portions, each of the first conductive portions being disposed on a corresponding one of the isolators opposite to a corresponding one of the etched first conductive pillars, each of the second conductive portions being disposed on a corresponding one of the isolators opposite to a corresponding one of the etched second conductive pillars.

A method for manufacturing a semiconductor memory device, comprising:

• forming a first dielectric stack region and a second dielectric stack region spaced apart from each other by a recess in a first direction;
• forming a separator in the recess;
• forming an array of repeating units which includes a first sub-array of the repeating units and a second sub-array of the repeating units respectively penetrating the first dielectric stack region and the second dielectric stack region, and being separated from each other by the separator, each of the repeating units including a first conductive pillar and a second conductive pillar which are spaced apart from each other by an isolation pillar in a second direction transverse to the first direction, and which extend upwardly in a third direction transverse to the first direction and the second direction, each of the first conductive pillars of the first sub-array being electrically connected to a corresponding one of the first conductive pillars of the second sub-array, and each of the second conductive pillars of the first sub-array being electrically connected to a corresponding one of the second conductive pillars of the second sub-array;
• partially etching the first conductive pillars of the repeating units in the first sub-array and the second conductive pillars of the repeating units in the second sub-array;
• forming a plurality of insulating portions on the etched first conductive pillars and the etched second conductive pillars, respectively;
• partially etching the insulating portions to form a plurality of isolators on the etched first conductive pillars and the etched second conductive pillars, respectively;
• and
• forming a plurality of first conductive portions and a plurality of second conductive portions, each of the first conductive portions being disposed on a corresponding one of the isolators opposite to a corresponding one of the etched first conductive pillars, each of the second conductive portions being disposed on a corresponding one of the isolators opposite to a corresponding one of the etched second conductive pillars.