Memory device with improved anti-fuse read current

A memory device comprising:

• a first programming gate-strip and a second programming gate-strip both extending in a second direction perpendicular to a first direction;
• a first read gate-strip and a second read gate-strip, both extending in the second direction, positioned between the first programming gate-strip and the second programming gate-strip;
• a first anti-fuse structure having a first dielectric layer overlying a first semiconductor region in an active zone at an intersection of the first programming gate-strip and the active zone extending in the first direction;
• a first transistor having a first channel region in the active zone at an intersection of the first read gate-strip and the active zone;
• a second anti-fuse structure having a second dielectric layer overlying a second semiconductor region in the active zone at an intersection of the second programming gate-strip and the active zone;
• a second transistor having a second channel region in the active zone at an intersection of the second read gate-strip and the active zone;
• a terminal conductor overlying a terminal region in the active zone between the first channel region of the first transistor and the second channel region of the second transistor;
• a group of first programming conducting lines, extending in the first direction, conductively connected to the first programming gate-strip through a first group of one or more gate via-connectors;
• a group of second programming conducting lines, extending in the first direction, conductively connected to the second programming gate-strip through a second group of one or more gate via-connectors;
• and
• a bit connector conductively connected to the terminal conductor through one or more terminal via-connectors.

A memory device comprising:

• a first programming gate-strip and a second programming gate-strip both extending in a second direction perpendicular to a first direction;
• a first read gate-strip and a second read gate-strip, both extending in the second direction, positioned between the first programming gate-strip and the second programming gate-strip;
• a first anti-fuse structure having a first dielectric layer overlying a first semiconductor region in an active zone at an intersection of the first programming gate-strip and the active zone extending in the first direction;
• a first transistor having a first channel region in the active zone at an intersection of the first read gate-strip and the active zone;
• a second anti-fuse structure having a second dielectric layer overlying a second semiconductor region in the active zone at an intersection of the second programming gate-strip and the active zone;
• a second transistor having a second channel region in the active zone at an intersection of the second read gate-strip and the active zone;
• a terminal conductor overlying a terminal region in the active zone between the first channel region of the first transistor and the second channel region of the second transistor;
• a group of first programming conducting lines, extending in the first direction, conductively connected to the first programming gate-strip through a first group of one or more gate via-connectors;
• a group of second programming conducting lines, extending in the first direction, conductively connected to the second programming gate-strip through a second group of one or more gate via-connectors;
• a first word programming line, extending in the second direction, conductively connected to the group of first programming conducting lines;
• and
• a second word programming line, extending in the second direction, conductively connected to the group of second programming conducting lines.