Apparatuses of controlling cross-layer reactions in semiconductor device
AssigneeMicron Technology, Inc.
InventorsAkie Shimamura, Kenichi Kusumoto
Life of this patent
Estimating the term…
Abstract
Apparatuses and methods for fabricating multilayer structures are described. An example method includes: forming a conductive base layer including silicon; forming a first conductive layer including first conductive material above the conductive base layer; forming a conductive barrier layer above the conductive layer; performing thermal loading to form a second conductive layer including silicide of the first conductive material between the conductive base layer and the conductive barrier layer; and forming a third conductive layer above the conductive barrier layer.
Claims18
An apparatus, comprising:
- a conductive base layer including silicon;
- a first conductive layer including silicide of a conductive material above the conductive base layer;
- a conductive barrier layer above the first conductive layer;
- and
- a second conductive layer above the conductive barrier layer,
- wherein the conductive barrier layer has a first thickness that is greater than a thickness of a first precursor conductive layer configured to form at least a lower portion of the conductive barrier layer and that is greater than a thickness of a second precursor conductive layer configured to form at least an upper portion of the conductive barrier layer,
- wherein the second conductive layer has a second thickness that is greater than a thickness of a third precursor conductive layer configured to form at least a lower portion of the second conductive layer and that is greater than a thickness of a fourth precursor conductive layer configured to form at least an upper portion of the second conductive layer, and
- wherein the second conductive layer includes ruthenium, the third precursor conductive layer includes ruthenium nitride, and the fourth precursor conductive layer includes ruthenium.
An apparatus, comprising:
- a memory cell array region including:
- a substrate;
- an isolation layer above the substrate;
- one or more word lines embedded between the substrate and the isolation layer;
- and
- a bit line on the isolation layer, including:
- a conductive base layer including silicon on the isolation layer;
- a first conductive layer including silicide of conductive material above the conductive base layer;
- a conductive barrier layer above the first conductive layer;
- and
- a second conductive layer as an electrode above the conductive barrier layer,
- wherein the conductive barrier layer has a first thickness that is greater than a thickness of a first precursor conductive layer configured to form at least a lower portion of the conductive barrier layer and that is greater than a thickness of a second precursor conductive layer configured to form at least an upper portion of the conductive barrier layer,
- wherein the second conductive layer has a second thickness that is greater than a thickness of a third precursor conductive layer configured to form at least a lower portion of the second conductive layer and that is greater than a thickness of a fourth precursor conductive layer configured to form at least an upper portion of the second conductive layer, and
- wherein the second conductive layer includes ruthenium, the third precursor conductive layer includes ruthenium nitride, and the fourth precursor conductive layer includes ruthenium.
Dependencies are inferred from the claim text.