Memory devices and methods of manufacturing thereof

A memory device, comprising:

• a plurality of memory cells arranged across a plurality of rows and a plurality of columns;
• wherein a first one of the memory cells is arranged at an intersection of one of the columns and a first one of the rows, and a second one of the memory cells is arranged at an intersection of the same column and a second one of the rows;
• wherein the first memory cell includes a first pull-down transistor and a second pull-down transistor, the first pull-down transistor and second pull-down transistor each having at least one of its metal contacts with a first depth extending into any of the first pull-down transistor and the second pull-down transistor from a top surface thereof greater than a depth of a metal contact extending into any other transistor included in the first memory cell;
• and
• wherein the second memory cell includes a third pull-down transistor and a fourth pull-down transistor, the third pull-down transistor and fourth pull-down transistor each having at least one of its metal contacts with a second depth extending into any of the third pull-down transistor and the fourth pull-down transistor from a top surface thereof greater than a depth of a metal contact extending into any other transistor included in the second memory cell.

A memory device, comprising:

• a plurality of memory cells arranged across a plurality of rows and a plurality of columns;
• wherein a first one of the memory cells is arranged at an intersection of one of the columns and a first one of the rows, and a second one of the memory cells is arranged at an intersection of the same column and a second one of the rows;
• wherein the first memory cell includes at least a first pull-down transistor, the first pull-down transistor having at least one of its metal contacts with a first depth extending into the first pull-down transistor, the first depth being greater than a depth of a metal contact of another transistor included in the first memory cell;
• and
• wherein the second memory cell includes at least a second pull-down transistor, the second pull-down transistor having at least one of its metal contacts with a second depth extending into the second pull-down transistor, the second depth being greater than a height of a metal contact of another transistor included in the second memory cell.