Light emitting element driving device

An LED dimming control device comprising a receiver configured to receive a predetermined communication signal transmitted across a communication line, the LED dimming control device being configured to perform programmable PWM dimming on individual LEDs using an internal PWM clock signal,

• wherein
• the predetermined communication signal is a UART communication signal, with each UART frame in a serial interface composed of one start bit and data bits,
• the internal PWM clock signal is adjusted by the predetermined communication signal,
• the predetermined communication signal is a signal in which a start bit with a first logic level is transmitted at a prescribed period from a transmitter and, as data bits succeeding each start bit, a signal with a second logic level is transmitted a predetermined number of times consecutively.

A light emitting element driving device comprising:

• a receiver configured to receive a predetermined communication signal transmitted across a communication line;
• a generator configured to generate a reference signal based on a start time point of a start bit in the predetermined communication signal;
• and
• a determiner configured to determine, based on the reference signal, timing of switching a light emitting element from OFF state to ON state,
• wherein the predetermined communication signal is a signal in which the start bit with a first logic level is transmitted at a prescribed period from a transmitter and in which data bits succeeding each start bit do not have a second logic level a predetermined number of times or more consecutively,
• wherein the generator includes:
• a detector configured to detect, as the start time point of the start bit, a first logic appearance time point at which the first logic level appears on the communication line for a first time after the period in which the communication line is at the second logic level has continued for a first predetermined time,
• wherein the detector is configured such that, if the period in which the communication line is at the first logic level does not continue for a second predetermined time after the first logic appearance time point, the detector exceptionally does not detect the first logic appearance time point as the start time point of the start bit.