US 12,192,665 B2 · Solid-state imaging device and imaging system

Abstract

A solid-state imaging device includes: a first semiconductor substrate including a photoelectric conversion element; and a second semiconductor substrate including at least a part of a peripheral circuit arranged in a main face of the second semiconductor substrate, the peripheral circuit generating a signal based on the charge of the photoelectric conversion element, a main face of the first semiconductor substrate and the main face of the second semiconductor substrate being opposed to each other with sandwiching a wiring structure therebetween; a pad to be connected to an external terminal; and a protection circuit electrically connected to the pad and to the peripheral circuit, wherein the protection circuit is arranged in the main face of the second semiconductor substrate.

Claims42

Dependent claims

A device comprising:

a first semiconductor substrate which includes a photoelectric conversion element;
a second semiconductor substrate which includes a transistor;
and
a wiring structure which is arranged between the first semiconductor substrate and the second semiconductor substrate,
wherein the first semiconductor substrate is provided with an opening,
wherein the second semiconductor substrate includes semiconductor regions and an insulating member,
wherein the semiconductor regions include a first semiconductor region and a second semiconductor region separated from the first semiconductor region by the insulating member, and
wherein the opening and at least one of the insulating member, the first semiconductor region and the second semiconductor regions overlap each other, or the opening and a poly silicon portion arranged between the wiring structure and the second semiconductor substrate overlap each other.

5 more elements

A device comprising:

a first semiconductor substrate which includes a photoelectric conversion element;
a second semiconductor substrate which includes a transistor;
a first wiring structure arranged between the first semiconductor substrate and the second semiconductor substrate;
and
a second wiring structure arranged between the first wiring structure and the second semiconductor substrate;
wherein the first semiconductor substrate is provided with an opening,
wherein the first wiring structure includes a plurality of first conductor portions and a first insulator portion, and, in a cross sectional view, the first insulator portion is arranged between one of the plurality of first conductor portions and another of the plurality of first conductor portions,
wherein the second wiring structure includes a plurality of second conductor portions and a second insulator portion, and, in the cross sectional view, the second insulator portion is arranged between one of the plurality of second conductor portions and another of the plurality of second conductor portions,
wherein in a bonding interface between the first wiring structure and the second wiring structure, the one of the plurality of first conductor portions and the one of the plurality of second conductor portions are bonded, the another of the plurality of first conductor portions and the another of the plurality of second conductor portions are bonded, and the first insulator portion and the second insulator portion are bonded,
wherein the one of the plurality of first conductor portions is electrically connected to a first wiring of the first wiring structure via a first plurality of vias, and
wherein the opening overlaps the one of the plurality of first conductor portions, the one of the plurality of second conductor portions and at least one of the first plurality of vias.

8 more elements

A device comprising:

a first semiconductor substrate which includes a photoelectric conversion element;
a second semiconductor substrate which includes a transistor;
a first wiring structure arranged between the first semiconductor substrate and the second semiconductor substrate;
and
a second wiring structure arranged between the first wiring structure and the second semiconductor substrate;
wherein the first semiconductor substrate is provided with an opening exposing a pad,
wherein the first wiring structure includes a plurality of first conductor portions and a first insulator portion, and, in a cross sectional view, the first insulator portion is arranged between one of the plurality of first conductor portions and another of the plurality of first conductor portions,
wherein the second wiring structure includes a plurality of second conductor portions and a second insulator portion, and, in the cross sectional view, the second insulator portion is arranged between one of the plurality of second conductor portions and another of the plurality of second conductor portions,
wherein in a bonding interface between the first wiring structure and the second wiring structure, the one of the plurality of first conductor portions and the one of the plurality of second conductor portions are bonded, the another of the plurality of first conductor portions and the another of the plurality of second conductor portions are bonded, and the first insulator portion and the second insulator portion are bonded,
wherein the pad is electrically connected to one of the plurality of first conductor portions, and
wherein the opening overlaps one of the plurality of first conductor portions.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/390,605Filed 30 Jul 2021 · continuation

Priority

JP 2010-14948430 Jun 2010

Published

US 2021/0360186 A118 Nov 2021

Granted

7 Jan 2025

Term ends

Not estimatedThe source records don’t support an estimate.

Classification14 codes

H04N 25/79
SSIS architectures; Circuits associated therewith: arrangements of circuitry being divided between different or multiple substrates, chips or…
H10D 89/611
For devices having insulated gate electrodes, e.g. for IGFETs or IGBTs: using diodes as protective elements
H10D 89/931
For devices having insulated gate electrodes, e.g. for IGFETs or IGBTs: characterised by the dispositions of the protective arrangements
H10F 39/014
Manufacture or treatment of image sensors covered by group H10F39/12: of CMOS image sensors

Family

PCT/JP2011/003570Parent of this continuation · filed 22 Jun 2011

Application14/992,234Parent of this continuation · filed 11 Jan 2016

US 9,252,169 B2Parent of this continuation · filed 2 Feb 2016

Application15/868,804Parent of this continuation · filed 11 Jan 2018

US 9,899,449 B2Parent of this continuation · filed 20 Feb 2018

US 10,304,899 B2Parent of this continuation · filed 23 Jan 2019

Application16/393,662Parent of this continuation · filed 24 Apr 2019

US 2021/0360186 A1Pre-grant publication · published 18 Nov 2021

US 11,102,440 B2Parent of this continuation

Application13/807,084Parent of this continuation

US 2013/0107075 A1Published application

US 2016/0126285 A1Published application

US 2018/0130847 A1Published application

US 2019/0252458 A1Published application

US 12,192,665 B2This patent

From the US filing history. Foreign family members aren’t listed.

Solid-state imaging device and imaging system

Life of this patent

Solid-state imaging device and imaging system

Life of this patent

Abstract

Claims42