A decoder, comprising a processor, a memory storing an instruction executable for the processor, a communication interface and a bus configured to connect the processor, the memory and the communication interface, wherein the processor is configured to perform, when running the instruction, operations of:
- determining a mode parameter of a current block;
- and
- in response to a determination that the mode parameter indicates that a prediction value of the current block is determined according to a matrix-based intra prediction (MIP) mode, performing prediction on the current block according to the MIP mode based on an initial right shift parameter, wherein the initial right shift parameter is an uniform offset parameter, and the offset parameter indicates a number of right shifting bits of the prediction value, wherein the offset parameter is set to be 6.