Monitoring circuit of phase locked loop and operating method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsDokyung Lim, Sounghun Shin, Wooseok Kim, Wonsik Yu, Chanyoung Jeong
Life of this patent
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Abstract
A monitoring circuit for a high frequency signal includes: a phase locked loop configured to generate a divided output signal with respect to an input signal based on a plurality of dividers; a plurality of dividing monitoring circuits configured to receive dividing input signals and dividing output signals respectively corresponding to the plurality of dividers, and output dividing error signals; and a jitter monitoring circuit configured to output a jitter error signal.
Claims20
A monitoring circuit comprising:
- a phase locked loop configured to generate an output signal by dividing an input signal based on a plurality of dividers;
- a plurality of dividing monitoring circuits, each dividing monitoring circuit being associated with a respective divider of the plurality of dividers and configured to receive a dividing input signal and a dividing output signal corresponding to the respective divider and to output a dividing error signal based on a dividing ratio range and a dividing ratio of the dividing output signal to the dividing input signal corresponding to the respective divider;
- and
- a jitter monitoring circuit configured to output a jitter error signal based on jitter of a signal generated in the phase locked loop and a jitter error range set in a calibration mode.
A method of monitoring a phase locked loop comprising a plurality of dividers, the method comprising:
- receiving dividing input signals and dividing output signals respectively corresponding to the plurality of dividers;
- outputting dividing error signals corresponding to respective divider of the plurality of dividers, based on a dividing ratio range and a dividing ratio of the dividing output signal to the dividing input signal corresponding to the respective divider;
- and
- outputting a jitter error signal based on jitter of a signal generated in the phase locked loop and a jitter error range set in a calibration mode.
A monitoring circuit for monitoring a phase locked loop comprising a plurality of dividers, the monitoring circuit comprising:
- a first dividing monitoring circuit configured to receive an input signal of the phase locked loop and a reference signal divided by an input signal divider, and output an input dividing error signal based on a first dividing ratio range and a first dividing ratio of the reference signal to the input signal;
- a second dividing monitoring circuit configured to receive an oscillating signal of the phase locked loop and a feedback signal divided by an oscillating signal divider, and output an oscillating dividing error signal based on a second dividing ratio range and a second dividing ratio of the feedback signal to the oscillating signal;
- a third dividing monitoring circuit configured to receive the oscillating signal of the phase locked loop and an output signal divided by an output signal divider, and output an output dividing error signal based on a third dividing ratio range and a third dividing ratio of the output signal to the oscillating signal;
- and
- a jitter monitoring circuit configured to output a jitter error signal based on jitter of the oscillating signal and a jitter error range set in a calibration mode.
Dependencies are inferred from the claim text.