Recovering scrambling sequence initialization from frozen bits of an uncoded downlink control information vector

A device, comprising:

• one or more memories;
• and
• one or more processors, coupled to the one or more memories, configured to:
• receive a downlink signal from a base station;
• determine an input-output relation of polar encoding based on an uncoded downlink control information vector of the downlink signal;
• perform an interleaving operation with a matrix and the input-output relation to obtain an interleaved vector;
• utilize rate matching with the interleaved vector to determine a scrambling sequence of the downlink signal;
• utilize a reverse sequence generator with the scrambling sequence to determine a scrambling sequence initialization vector for the scrambling sequence;
• and
• decode the downlink signal based on the scrambling sequence initialization vector and without performing a descrambling operation.

A non-transitory computer-readable medium storing a set of instructions, the set of instructions comprising:

• one or more instructions that, when executed by one or more processors of a device, cause the device to:
• receive a downlink signal from a base station,
• wherein the downlink signal includes one of:
• a physical broadcast channel signal, or
• a physical downlink control channel signal;
• determine an input-output relation of polar encoding based on a vector of the downlink signal;
• perform an interleaving operation with a matrix and the input-output relation to obtain an interleaved vector;
• utilize rate matching with the interleaved vector to determine a scrambling sequence of the downlink signal;
• utilize a reverse sequence generator with the scrambling sequence to determine a scrambling sequence initialization vector for the scrambling sequence;
• and
• decode the downlink signal based on the scrambling sequence initialization vector and without performing a descrambling operation.