Early detection of single bit error on address and data

A circuit comprising:

• an error correction code (ECC) calculation circuit that calculates an ECC having ECC bits computed using a plurality of bits pointing to a memory address, a plurality of bits representative of data stored in each memory address, and a plurality of received pad bits;
• wherein the plurality of memory address bits, the plurality of bits representative of the data, the plurality of received pad bits and the ECC bits define a bit pattern;
• a syndrome calculation circuit that generates a plurality of syndrome values each associated with a different one of the ECC bits, the address bits and the data bits;
• wherein a syndrome value of the plurality of syndrome values is associated with a respective bit in the bit pattern, and
• wherein the syndrome value corresponds to a plurality of syndrome value bits;
• and
• a comparator that detects an error in the address bits or the data bits using a subset of bits representing a maximum of the plurality of syndrome values.

A non-transitory computer readable storage medium comprising stored instructions, which when executed by a processor, cause the processor to:

• determine a number of address bits in an address of the memory, and a number of data bits stored in a corresponding address of the memory;
• determine a sum defined by the number of address bits, the number of data bits, and a number of error correction code (ECC) bits computed using the memory address bits and the memory data bits;
• determine a maximum syndrome value from the sum;
• responsive to a determination that the maximum syndrome value is greater than the sum:
• insert a logic value into each bit position corresponding to a syndrome value without a corresponding address bit, data bit, or ECC bit, wherein the address bits, the data bits data, the ECC bits, and bits representative of the inserted logic values define a bit pattern;
• determine a plurality of syndrome values using the address bits, the data bits, and the ECC bits;
• wherein a syndrome value of the plurality of syndrome values is associated with a respective bit in the bit pattern, and
• wherein the syndrome value corresponds to a plurality of syndrome value bits;
• and
• use a subset of bits representing the plurality of syndrome values to detect an error.