Multi-bit voltage-to-delay conversion in data converter circuitry

A method of converting an analog signal level to a digital word, comprising the steps of:

• sampling a differential input signal;
• generating, from the sampled input signal, a plurality of differential residue signals relative to a plurality of zero-crossing references;
• chopping each of the differential residue signals;
• applying each chopped differential residue signal to a corresponding one of a plurality of zero-crossing comparators in an ordered sequence of zone thresholds;
• identifying an input range zone for the sampled input signal between the zone thresholds of neighboring comparators in the ordered sequence having a change in polarity at their outputs;
• identifying a delay between logic transitions at the neighboring comparators;
• and
• encoding a digital output word indicating the identified input range zone and the identified delay.

A voltage-to-delay conversion circuit, comprising:

• a multi-bit input buffer having a differential input adapted to receive a differential input sample, and configured to generate, at a plurality of differential outputs, a plurality of residues of the input sample relative to a corresponding plurality of zero-crossing references, the multi-bit input buffer including:
• first and second resistor ladders, each comprising a plurality of resistors connected in series;
• first and second transistors, the first transistor having a conduction path between a power supply terminal and the first resistor ladder, the second transistor having a conduction path between the first resistor ladder and a ground terminal, each of the first and second transistors having a control terminal coupled to a first input of the differential input;
• and
• third and fourth transistors, the third transistor having a conduction path between the power supply terminal and the second resistor ladder, the fourth transistor having a conduction path between the first resistor ladder and the ground terminal, each of the third and fourth transistors having a control terminal coupled to a second input of the differential input;
• wherein each the plurality of differential outputs comprises a terminal in the first resistor ladder and a corresponding opposing terminal in the second resistor ladder;
• a plurality of zero-crossing comparators, each having a differential input adapted to receive one of the residues from one of the differential outputs of the input buffer and having an output, each zero-crossing comparator associated with a zone threshold according to an ordered sequence of zone thresholds, so that the outputs of the zero-crossing comparators indicate an input range zone of the input sample between the zone thresholds associated with neighboring comparators in the ordered sequence having different polarities at their outputs;
• and
• folding logic circuitry, having a plurality of inputs, each coupled to the output of one of the comparators, and configured to output a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold.

An analog-to-digital converter having an analog input adapted to receive an analog input signal and having an output adapted to output a digital signal including most-significant bits (MSBs) and least-significant bits (LSBs), the analog-to-digital converter comprising:

• a multi-bit input buffer having a buffer input coupled to the analog input and having a plurality of buffer outputs;
• a V2D comparator stage having a plurality of V2D inputs, each coupled to a different one of the plurality of buffer outputs and having a plurality of V2D outputs, the V2D comparator stage including:
• a plurality of mixers each having a mixer input, a mixer output, and a mixer-chopper input, each mixer input coupled to one of the plurality of V2D inputs and each mixer-chopper input coupled to chopper circuitry configured to generate a pseudo-random binary sequence;
• and
• a plurality of comparators each having a comparator input, a comparator output and comparator-chopper input, each comparator input coupled to a corresponding mixer output and each comparator-chopper input coupled to the chopper circuitry, the plurality of comparators configured to output the MSBs of the digital signal;
• and
• a folding circuit having a plurality of folding circuit inputs, a plurality of folding circuit outputs, and a plurality of logic gates coupled therebetween, each folding circuit input coupled to a respective comparator output and the folding circuit configured to output the LSBs of the digital signal.