Frequency-locked and phase-locked loop-based clock glitch detection for security
AssigneeNVIDIA Corporation
InventorsSanquan Song, Stephen G. Tell, Nikola Nedovic
Life of this patent
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Abstract
A glitch detection device includes an oscillator to generate multiple local clocks of multiple different phases and a sampling circuit to oversample, using the multiple local clocks, a system clock to generate multiple samples of the system clock. The device further includes a glitch detector to monitor a variation in pulse width of the system clock based on counting the multiple samples and to report a glitch in response to detecting a variation in the pulse width that exceeds a threshold value.
Claims23
A glitch detection device comprising:
- an oscillator to generate multiple local clocks of multiple different phases;
- a sampling circuit to oversample, using the multiple local clocks, a system clock to generate multiple samples of the system clock;
- and
- a glitch detector coupled to the sampling circuit, the glitch detector to:
- monitor a variation in pulse width of the system clock based on counting the multiple samples;
- and
- report a glitch in response to detecting a variation in the pulse width that exceeds a threshold value.
A computing system comprising:
- an external oscillator that generates a system clock;
- and
- a die coupled to the external oscillator, the die comprising:
- an internal oscillator to generate multiple local clocks of multiple different phases;
- a sampling circuit to oversample, using the multiple local clocks, the system clock to generate multiple samples of the system clock;
- and
- a glitch detector coupled to the sampling circuit, the glitch detector to:
- monitor a variation in pulse width of the system clock based on counting the multiple samples;
- and
- report a glitch in response to detecting a variation in the pulse width exceeds a threshold value.
A method of operating a glitch detection circuit comprising an oscillator, a sampling circuit, and digital logic for controlling the oscillator, the method of operating the glitch detection circuit comprising a plurality of operations comprising:
- generating, by the oscillator, multiple local clocks of multiple different phases;
- oversampling, by the sampling circuit using the multiple local clocks, a system clock to generate multiple samples of the system clock;
- monitoring, by a glitch detector of the digital logic, a variation in pulse width of the system clock based on counting the multiple samples;
- and
- reporting, by the glitch detector, a glitch in response to detecting a variation in the pulse width that exceeds a threshold value.
Dependencies are inferred from the claim text.