Back to results
US 12,191,865 B2Granted
Phase lock loop (PLL) synchronization
AssigneeSpace Exploration Technologies Corp.
InventorsDavid Francois Jacquet, Mostafa Ghazali, Masoud Kahrizi, Andras Tantos
Life of this patent
Estimating the term…
Abstract
In an embodiment, an apparatus includes one or more timing components configured to generate a reference time signal based on a timing signal and a reference clock signal. The apparatus includes phase lock loop (PLL) configured to generate a synchronized output clock signal based on the reference clock signal and the reference time signal.
Claims25
An apparatus comprising:
- one or more timing components configured to generate a reference time signal based on a timing signal and a reference clock signal;
- and
- a phase lock loop (PLL) configured to generate a synchronized output clock signal based on the reference clock signal and the reference time signal, wherein one or more timing components are configured to generate a synchronization signal to trigger phase synchronization of the PLL if the reference time signal equals a pre-set reference time signal count value and the PLL is in a locked state.
An apparatus comprising:
- a phase lock loop (PLL), wherein the PLL includes a sigma delta modulator (SDM), and wherein the PLL is configured to generate an output clock signal based on a reference clock signal, wherein the SDM is reset based on the reference clock signal, a timing signal, and a reference time signal;
- and
- one or more timing components configured to generate the reference time signal based on a timing signal and the reference clock signal;
- and a clock PLL configured to generate and provide a second reference clock signal at a higher frequency than the reference clock signal, wherein:
- the one or more timing components are configured to generate a second reference time signal based on the reference time signal and the second reference clock signal;
- the second reference time signal specifies a count of a number of cycles of the second reference clock signal starting from a particular cycle of the second reference clock signal;
- and
- the SDM is reset based on the second reference time signal.
5 more elements
An apparatus comprising:
- a phase lock loop (PLL), wherein the PLL includes a sigma delta modulator (SDM), wherein the PLL is configured to generate an output clock signal based on a reference clock signal, wherein the SDM is reset based on the reference clock signal, a timing signal, and a reference time signal, and wherein the reference clock signal comprises a first reference clock signal and the PLL is configured to generate an output clock signal based on a reference clock signal;
- a counter configured to generate, based on a timing signal and the first reference clock signal, a first reference time signal indicative of a count of periods of the first reference clock signal;
- a second reference clock configured to generate a second reference clock signal having a second frequency different from a first frequency associated with the first reference clock signal;
- a clock generator configured to generate, based on the first reference clock signal, the second reference clock signal, and a phase selection, a third reference clock signal having a third frequency, wherein at least one or more of the third frequency or a phase shift of the third reference clock signal is different from the second reference clock signal;
- and
- a second counter configured to generate a third reference time signal indicative of sub-periods of the third reference clock signal in accordance with the phase selection, wherein the SDM is reset using the third reference time signal.
3 more elements
Dependencies are inferred from the claim text.