Apparatuses and methods for duty cycle adjustment

A duty cycle adjustment circuit of a dynamic random access memory (DRAM), comprising:

• an adjustment circuit, comprising a duty cycle adjuster comprising a plurality of adjustor cells, wherein the duty cycle adjustor is configured to receive a clock signal and to adjust a duty cycle of the clock signal using the plurality of adjustor cells to provide a duty cycle adjusted clock signal, wherein each of a first serially-coupled subset of the plurality of adjustor cells is configured to apply only a respective coarse adjustment to the duty cycle of the clock signal and each of a second serially-coupled subset of the plurality of adjustment cells non-overlapping with the first serially-coupled subset is configured to apply both a respective fine adjustment to the duty cycle of the clock signal and the respective coarse adjustment to the duty cycle of the clock signal, wherein a first one of the first serially-coupled subset of the plurality of adjustor cells is configured to receive the clock signal simultaneous with receipt of the clock signal at a first one of the second serially-coupled subset of the plurality of adjustor cells, wherein an adjustor cell of the second subset of the plurality of adjuster cells comprises a first transistor having a first size for providing a coarse adjustment and a second transistor having a second size for providing a fine adjustment, wherein the first size and the second size are different;
• and
• recovery control logic configured to enable sequential selection of coarse and fine adjustment values to apply to the clock signal by the duty cycle adjustor during a duty cycle adjustment selection operation, wherein the recovery control logic receives an enable signal from a memory controller in communication with the DRAM.

A method, comprising:

• receiving an enable signal from a memory controller at a duty cycle adjustment circuit of a dynamic random access memory (DRAM);
• enabling the duty cycle adjustment circuit responsive to the enable signal;
• receiving a clock signal at a duty cycle adjustor of the duty cycle adjustment circuit;
• applying a coarse adjustment to the duty cycle of the clock signal based on a respective coarse adjustment value using an adjustor cell selected from a first serially-coupled subset of less than all of a plurality of adjustor cells of the duty cycle adjustor that are each configured to apply both a portion of the coarse adjustment and a portion of a fine adjustment to the duty cycle of the clock signal based on a respective fine adjustment value,
• wherein an adjustor cell of the first serially-coupled subset comprises a first transistor having a first size for providing a coarse adjustment and a second transistor having a second size for providing a fine adjustment, wherein the first size and the second size are different,
• wherein a second serially-coupled subset of the plurality of adjustor cells non-overlapping with the first subset are each only configured to apply the coarse adjustment, wherein a first one of the first serially-coupled subset of the plurality of adjustor cells is configured to receive the clock signal simultaneous with receipt of the clock signal at a first one of the second serially-coupled subset of the plurality of adjustor cells;
• and
• applying the fine adjustment of the duty cycle of the clock signal based on the respective fine adjustment value using at least the adjustor cell of the plurality of adjustor cells of the duty cycle adjustor;
• and
• during a duty cycle adjustment selection operation, selecting the respective fine adjustment value to apply to the clock signal to perform the fine adjustment of the duty cycle of the clock signal after completion of selection of the respective coarse adjustment value to apply to the clock signal to perform the coarse adjustment of the duty cycle of the clock signal.