Level shifter circuit and method of operating the same

An integrated circuit comprising:

• an input circuit coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second input signal or a third input signal, the input circuit comprising:
• a first set of transistors having a first threshold voltage, the first set of transistors comprising:
• a first set of active regions extending in a first direction;
• and
• a level shifter circuit coupled to at least the input circuit and a second voltage supply different from the first voltage supply, and configured to receive at least a first enable signal, the second input signal or the third input signal, and to generate at least a first signal responsive to at least the first enable signal, the second input signal or the third input signal, the level shifter circuit comprising:
• a second set of transistors having a second threshold voltage, the second set of transistors comprising:
• a second set of active regions extending in the first direction, and being separated from the first set of active regions in a second direction different from the first direction.

An integrated circuit comprising:

• an input circuit coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second input signal or a third input signal, the input circuit comprising:
• a first set of transistors having a first threshold voltage, the first set of transistors comprising:
• a first set of active regions extending in a first direction;
• a level shifter circuit coupled to at least the input circuit and a second voltage supply different from the first voltage supply, and configured to receive at least a first enable signal, the second input signal or the third input signal, and to generate at least a first signal responsive to at least the first enable signal, the second input signal or the third input signal, the level shifter circuit comprising:
• a second set of transistors having a second threshold voltage, the second set of transistors comprising:
• a second set of active regions extending in the first direction, and being separated from the first set of active regions in a second direction different from the first direction;
• and
• a third set of transistors having a third threshold voltage different from the first threshold voltage and the second threshold voltage, the third set of transistors comprising:
• a third set of active regions extending in the first direction, and being separated from the first set of active regions and the second set of active regions in the second direction;
• and
• an output circuit coupled to at least the level shifter circuit and the second voltage supply, and configured to generate at least an output signal responsive to the first signal, the output circuit comprising:
• a fourth set of transistors having the second threshold voltage, the fourth set of transistors comprising:
• a fourth set of active regions extending in the first direction, and being separated from the first set of active regions in the second direction.