Method and system of operating a gate driver
AssigneeSemiconductor Components Industries, LLC
InventorsKarel Ptacek, Jaroslav Knop
Life of this patent
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Abstract
Operating a gate driver. At least one example is a method of operating the gate driver, the method comprising: de-asserting a drive-low terminal of the gate driver; starting a single timer within the gate driver; and after expiration of the single timer asserting a drive-high terminal of the gate driver responsive to assertion of an in-high terminal of the gate driver; and then de-asserting the drive-high terminal; starting the single timer; and after a second expiration of the single timer asserting the drive-low terminal responsive to assertion of an in-low terminal of the gate driver.
Claims20
A method of operating a gate driver, the method comprising:
- de-asserting a drive-low terminal of the gate driver;
- starting a single timer within the gate driver;
- and after expiration of the single timer
- asserting a drive-high terminal of the gate driver responsive to assertion of an in-high terminal of the gate driver;
- and then
- de-asserting the drive-high terminal;
- starting the single timer;
- and after a second expiration of the single timer
- asserting the drive-low terminal responsive to assertion of an in-low terminal of the gate driver.
A gate driver, comprising:
- an in-high terminal, an in-low terminal, a drive-high terminal, and a drive-low terminal;
- a high-side amplifier defining a drive output coupled to the drive-high terminal, and a drive input;
- a low-side amplifier defining a drive output coupled to the drive-low terminal, and a drive input;
- a timer defining a timer-start input, and a timer-end output;
- a controller coupled to the in-high terminal, the in-low terminal, the drive input of the high-side amplifier, the drive input of the low-side amplifier, the timer-start input, and the timer-end output, the controller configured to:
- insert a first delay time between de-assertion of the drive-high terminal and assertion of the drive-low terminal, the insertion of the first delay time based on the timer-end output;
- and
- insert a second delay time between de-assertion of the drive-low terminal and assertion of the drive-high terminal, the insertion of the second delay time based on the timer-end output.
A power converter comprising:
- a high-side FET defining a drain coupled to a voltage input, a source defining a switch node, and a gate;
- a low-side FET defining a drain coupled to the switch node, a source coupled to a reference voltage, and a gate;
- an inductance coupled to the switch node;
- a rectifier coupled to the inductance;
- a gate driver defining an in-high terminal, an in-low terminal, a drive-high terminal coupled to the gate of the high-side FET, and a drive-low terminal coupled to the gate of the low-side FET;
- a converter controller coupled to the in-high terminal and the in-low terminal, the converter controller configured to alternately assert the in-high terminal and the in-low terminal;
- the gate driver configured to:
- insert a first delay time between de-assertion of the drive-high terminal and assertion of the drive-low terminal based on a timer within the gate driver, and
- insert a second delay time between de-assertion of the drive-low terminal and assertion of the drive-high terminal based on the timer.
Dependencies are inferred from the claim text.