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US 12,191,815 B2Granted
Sub-micron CMOS high-power cascode RF power amplifier
AssigneeRenesas Electronics America Inc.
InventorsMorteza Abbasi, Tumay Kanar, Naveen Krishna Yanduru
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Abstract
An apparatus includes an amplifier circuit including a first transistor and a second transistor. The first transistor may include a gate having a gate oxide with a first thickness and a first gate length. The second transistor may include a gate having a gate oxide with a second thickness and a second gate length. The first transistor and the second transistor may be connected in a cascode configuration and the second thickness and the second gate length are greater than the first thickness and the first gate length, respectively.
Claims17
An apparatus comprising:
- a first transistor comprising a gate having a gate oxide with a first thickness and a first gate length, the first transistor being configured as a common source amplifier stage;
- a second transistor comprising a gate having a gate oxide with a second thickness and a second gate length, the second transistor being configured as a common gate amplifier stage;
- a metal strip disposed on top of a gate of the first transistor;
- and
- a set of vias placed on the metal strip to tap the gate of the first transistor,
- wherein:
- the set of vias are placed at points along the metal strip and outside of active regions of the first transistor;
- the first transistor and the second transistor are connected in a cascode configuration;
- the second thickness is greater than the first thickness;
- and
- the second gate length is greater than the first gate length.
8 more elements
An apparatus comprising:
- a first bias circuit configured to output a first bias voltage;
- a second bias circuit configured to output a second bias voltage;
- a first amplifier circuit and a second amplifier circuit, each one of the first and second amplifier circuits comprises:
- a first transistor comprising a gate having a gate oxide with a first thickness and a first gate length, the first transistor being configured as a common source amplifier stage;
- and
- a second transistor comprising a gate having a gate oxide with a second thickness and a second gate length the second transistor being configured as a common gate amplifier stage;
- a metal strip disposed on top of a gate of the first transistor;
- and
- a set of vias placed on the metal strip to tap the gate of the first transistor, wherein:
- the set of vias are placed at points along the metal strip and outside of active regions of the first transistor;
- the first transistor and the second transistor are connected in a cascode configuration;
- the second thickness is greater than the first thickness;
- the second gate length is greater than the first gate length;
- and
- each one of the first amplifier circuit and the second amplifier circuit is configured to:
- receive an input signal biased by the first bias voltage;
- receive the second bias voltage to drive a gate of the second transistor;
- and
- output an output signal that is an amplified version of the input signal.
16 more elements
An apparatus comprising:
- a phased antenna array;
- a communication circuit connected to the phased antenna array, wherein a power amplifier stage of the communication circuit comprises:
- a first bias circuit configured to output a first bias voltage;
- a second bias circuit configured to output a second bias voltage;
- a first amplifier circuit and a second amplifier circuit, each one of the first and second amplifier circuits comprises:
- a first transistor comprising a gate having a gate oxide with a first thickness and a first gate length, the first transistor being configured as a common source amplifier stage;
- a second transistor comprising a gate having a gate oxide with a second thickness and a second gate length the second transistor being configured as a common gate amplifier stage;
- a metal strip disposed on top of a gate of the first transistor;
- and
- a set of vias placed on the metal strip to tap the gate of the first transistor, wherein:
- the set of vias are placed at points along the metal strip and outside of active regions of the first transistor;
- the first transistor and the second transistor are connected in a cascode configuration,
- the second thickness is greater than the first thickness;
- the second gate length is greater than the first gate length:
- each one of the first amplifier circuit and the second amplifier circuit is configured to:
- receive an input signal biased by the first bias voltage;
- receive the second bias voltage to drive a gate of the second transistor;
- and
- output an output signal to the phased antenna array, wherein the output signal is an amplified version of the input signal.
16 more elements
Dependencies are inferred from the claim text.