Low I/O current sharing architecture for multiphase DC-DC converters

A multi-phase converter system, comprising:

• two or more power stage chips, wherein each power stage chip further comprises:
• a pulse-width modulation (PWM) pin;
• a powering voltage input (PVIN) pin;
• a ground (GND) pin;
• a switching node (SW) pin;
• two internal switches controlled by a PWM signal of a multiphase controller chip to produce the desired PWM signal at the SW pin;
• a driver circuit;
• a current monitoring (IMON) pin;
• a first current mirror circuit to output a current through the IMON pin that is proportional to the current through the SW pin;
• a second current mirror circuit to produce a current that is proportional to the current flow through the SW pin of the power stage chips;
• a resistor Rint, located either outside or inside the power stage chip, to allow the current of the second current mirror circuit to flow through to generate a voltage signal:
• Vint;
• a circuit to compare the Vint and the voltage on the IMON pin, and generate an ADJUST signal;
• and
• a PWM adjust block to adjust the PWM signal according to the ADJUST signal;
• the multi-phase controller chip to generate multiple PWM signals, wherein the multi-phase controller chip further comprises a pin connected to all the IMON pins of all the power stage chips to measure an analog signal;
• two or more inductors, wherein one terminal of each inductor is connected to the SW pin while the other terminal of all the inductors is connected together to form an output terminal:
• Vout;
• a ground terminal;
• and
• one or more output voltage filter capacitors, wherein the output voltage filter capacitor is connected between the Vout and the ground terminal for filtering out the high frequency current ripple and can be implemented by one single output voltage filter capacitor or by paralleling multiple output voltage filter capacitors.