Circuit and method for high voltage tolerant ESD protection
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsLi-Wei Chu, Tao Yi Hung, Chia-Hui Chen, Wun-Jie Lin, Jam-Wem Lee
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Abstract
In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.
Claims20
An electrostatic discharge (ESD) protection circuit, comprising:
- a plurality of first transistors coupled between a pad and a ground;
- and
- at least one second transistor and an ESD clamp coupled between at least one of the plurality of first transistors and the ground, wherein a gate of the at least one second transistor is coupled to the ground.
An electrostatic discharge (ESD) protection circuit comprising:
- a plurality of first transistors coupled between a pad and a ground;
- a plurality of switches, each coupled to one of the plurality of first transistors;
- and
- at least one second transistor and an ESD clamp coupled between one of the plurality of switches and the ground.
A method for operating an electrostatic discharge (ESD) protection circuit, comprising:
- receiving, at a pad coupled to one of a plurality of first transistors, an ESD voltage, enabling at least one second transistor coupled to one of the plurality of first transistors and an ESD clamp coupled to the at least one second transistor;
- and
- discharging a first current associated with the ESD voltage through the at least one second transistor and ESD clamp.
Dependencies are inferred from the claim text.