Low Ge isolated epitaxial layer growth over nano-sheet architecture design for RP reduction

A nano-FET comprising:

• a substrate;
• a first nanostructure and a second nanostructure over the substrate in a stack;
• an epitaxial source/drain region contacting ends of the first nanostructure and the second nanostructure, the epitaxial source/drain region comprising:
• a first semiconductor material layer comprising a first semiconductor material, the first semiconductor material layer comprising a first segment contacting the first nanostructure, a second segment contacting the second nanostructure, and a third segment contacting a recessed portion of the substrate, wherein the first segment, the second segment, and the third segment are each discontinuous from each other;
• and
• a second semiconductor material layer over the first segment, the second segment, and the third segment, the second semiconductor material layer comprising a second semiconductor material, wherein the second semiconductor material layer has a higher concentration of dopants of a first conductivity type than the first semiconductor material layer, wherein the second semiconductor material layer and the first semiconductor material layer are silicon-based materials, wherein the second semiconductor material layer has a lower concentration percentage of silicon than the first semiconductor material layer;
• and
• a gate electrode between the first nanostructure and the second nanostructure, wherein a spacer separates the gate electrode from the epitaxial source/drain region, the spacer being further disposed between the first nanostructure and the second nanostructure;
• wherein interfaces between the first nanostructure and the first segment, and the second nanostructure and the first segment, have a shape curving inwards away from the epitaxial source drain region at the center.

A method for forming a nano-FET, the method comprising:

• forming a plurality of nanostructure layers comprising alternating layers of a first semiconductor material and a second semiconductor material;
• forming a first recess in the plurality of nanostructure layers to form a stack of a plurality of first nanostructures, ends of the plurality of first nanostructures being exposed in the first recess;
• recessing ends of the plurality of first nanostructures of the second semiconductor material to form a second recess;
• forming inner spacers in the second recess on the ends of the plurality of first nanostructures of the second semiconductor material;
• forming source/drain regions in the first recess, wherein forming the source/drain regions comprising:
• epitaxially growing a first semiconductor material layer on each end of the plurality of first nanostructures of the first semiconductor material and on an exposed and recessed portion of a semiconductor substrate adjacent to the plurality of first nanostructures, wherein the first semiconductor material layer is discontinuous between growth on a first plurality of end of the plurality of first nanostructures and the exposed portion of the semiconductor substrate, wherein the first semiconductor material layer is merged across a second plurality of ends of the first plurality of first nanostructures;
• and
• epitaxially growing a second semiconductor material layer over each of the first semiconductor material layers, wherein the first semiconductor material layer has a lower concentration of dopants of a first conductivity type than the second semiconductor material layer.