US 12,191,390 B2 · Semiconductor device including stacked semiconductor patterns

Abstract

A semiconductor device including a substrate that includes first to third regions; a first channel structure on the first region and including first channel patterns that are vertically stacked on the substrate; a second channel structure on the second region and including a second channel pattern on the substrate; a third channel structure on the third region and including third channel patterns and fourth channel patterns that are vertically and alternately stacked on the substrate; first to third gate electrodes on the first to third channel structures; and first to third source/drain patterns on opposite sides of the first to third channel structures, wherein the first, second, and fourth channel patterns include a first semiconductor material, and the third channel patterns include a second semiconductor material different from the first semiconductor material.

Claims20

Dependent claims

A semiconductor device, comprising:

a substrate that includes a first region, a second region, and a third region;
a plurality of first semiconductor patterns that are vertically stacked on the first region;
a second semiconductor pattern on the second region;
a plurality of third semiconductor patterns and a plurality of fourth semiconductor patterns that are vertically and alternately stacked on the third region;
a first electrode on the plurality of first semiconductor patterns, a second electrode on the second semiconductor pattern, and a third electrode on the plurality of third semiconductor patterns;
and
a first source/drain pattern on opposite sides of the plurality of first semiconductor patterns,
wherein:
the plurality of first semiconductor patterns, the second semiconductor pattern, and the plurality of fourth semiconductor patterns each include a first semiconductor material, and
the plurality of third semiconductor patterns include a second semiconductor material different from the first semiconductor material.

7 more elements

A semiconductor device, comprising:

a substrate that includes a first region, a second region, and a third region;
a first structure on the first region, the first structure including a plurality of first semiconductor patterns that are vertically stacked on the substrate;
a second structure on the second region, the second structure including a second semiconductor pattern on the substrate;
a third structure on the third region, the third structure including a plurality of third semiconductor patterns and a plurality of fourth semiconductor patterns that are vertically and alternately stacked on the substrate;
a first electrode on the first structure, a second electrode on the second structure, and a third electrode on the third structure;
a first dielectric layer between the first electrode and the first structure, a second dielectric layer between the second electrode and the second structure, and a third dielectric layer between the third electrode and the third structure;
and
first source/drain patterns on opposite sides of the first structure and second source/drain patterns on opposite sides of the second structure,
wherein:
the third structure has an uneven sidewall, and
the third dielectric layer covers the uneven sidewall.

8 more elements

A semiconductor device, comprising:

a substrate that includes a first region, a second region, and a third region;
a first structure on the first region, the first structure including a plurality of first semiconductor patterns that are vertically stacked on the substrate;
a second structure on the second region, the second structure including a second semiconductor pattern on the substrate;
a third structure on the third region, the third structure having an uneven sidewall and including a plurality of third semiconductor patterns and a plurality of fourth semiconductor patterns that are vertically and alternately stacked on the substrate;
a first electrode on the first structure, a second electrode on the second structure, and a third electrode on the third structure;
a first dielectric layer between the first electrode and the first structure, a second dielectric layer between the second electrode and the second structure, and a third dielectric layer between the third electrode and the third structure;
and
a first source/drain pattern on opposite sides of the first structure, a second source/drain pattern on opposite sides of the second structure, and a third source/drain pattern on opposite sides of the third structure,
wherein:
the plurality of first semiconductor patterns, the second semiconductor pattern, and the plurality of fourth semiconductor patterns each include silicon, and
the plurality of third semiconductor patterns each include silicon-germanium.

8 more elements

Dependencies are inferred from the claim text.

Semiconductor device including stacked semiconductor patterns

Life of this patent

Semiconductor device including stacked semiconductor patterns

Life of this patent

Abstract

Claims20