Layered structure, semiconductor device including the same, and manufacturing method thereof

A semiconductor device, comprising:

• a field-effect transistor, comprising:
• a gate structure disposed on a semiconductor channel of a semiconductor substrate;
• a source region and a drain region disposed in the semiconductor substrate at opposite ends of the semiconductor channel;
• an interlayer dielectric layer disposed on the semiconductor substrate and surrounding the gate structure;
• and
• a source contact and a drain contact extending through the interlayer dielectric layer to contact the source region and the drain region, wherein top surfaces of the source contact and the drain contact are flushed with a top surface of the gate structure;
• a thin film transistor disposed over and electrically to the field-effect transistor, and comprising a channel pattern comprising a semiconductor oxide;
• and
• a ferroelectric tunnel junction, disposed over and electrically connected to the thin film transistor, wherein the ferroelectric tunnel junction comprises:
• a bottom electrode and a top electrode;
• and
• a layered structure, disposed between the bottom electrode and the top electrode and comprising at least two crystalline oxide layers and at least two ferroelectric layers stacked alternately and in direct contact with each other, wherein each ferroelectric layer is hafnium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, hafnium aluminum oxide, or hafnium silicon oxide, and a topmost layer and a bottommost layer are both crystalline oxide layers, wherein each of the bottom electrode and the top electrode is TiN, TaN, or a combination thereof, and the bottommost crystalline oxide layer of the layered structure is in direct contact with the bottom electrode, and wherein a topmost ferroelectric layer of the layered structure is in direct contact with the top electrode.

A semiconductor device, comprising:

• a field-effect transistor, comprising:
• a gate structure disposed on a semiconductor channel of a semiconductor substrate;
• a source region and a drain region disposed in the semiconductor substrate at opposite ends of the semiconductor channel;
• an interlayer dielectric layer disposed on the semiconductor substrate and surrounding the gate structure;
• and
• a source contact and a drain contact extending through the interlayer dielectric layer to contact the source region and the drain region, wherein top surfaces of the source contact and the drain contact are flushed with a top surface of the gate structure;
• a thin film transistor disposed over and electrically to the field-effect transistor, and comprising:
• a channel pattern comprising a semiconductor oxide;
• a gate pattern disposed over the channel pattern;
• and
• two contacts disposed over the channel pattern and beside the gate pattern, wherein top surfaces of the two contacts are flushed with a top surface of the gate pattern, the high-k dielectric pattern is disposed only between facing inner sidewalls of the contacts, and a width of the high-k dielectric pattern is less than a width of the channel pattern, and sidewalls of the channel pattern are respectively flushed with outer sidewalls of the contacts;
• and
• a ferroelectric tunnel junction electrically connected to one of the contacts of the second transistor, wherein the ferroelectric tunnel junction comprises:
• a first electrode;
• a second electrode, disposed over the first electrode;
• and
• a layered structure comprising at least two crystalline oxide layers and at least two ferroelectric layers disposed alternately and in direct contact with each other between the first electrode and the second electrode, wherein each of the first electrode and the second electrode is TiN, TaN, or a combination thereof, and the bottommost crystalline oxide layer of the layered structure is in direct contact with the first electrode, and wherein a topmost ferroelectric layer of the layered structure is in direct contact with the second electrode.