Area scaling for VTFET contacts

A vertical transport field effect transistor (VTFET) device, comprising:

• at least one fin serving as a vertical fin channel of the VTEFT device;
• a bottom source/drain region present at a base of the at least one fin;
• a gate stack alongside the at least one fin, wherein the gate stack extends along a vertical sidewall of the at least one fin;
• a top source/drain region present at a top of the at least one fin;
• an encapsulation layer located on top of and along a vertical side of the gate stack that extends along a vertical sidewall of the at least one fin, wherein the encapsulation layer is located adjacent to the top source/drain region;
• a bottom spacer located adjacent to the sidewalls of the at least one fin, wherein the gate stack is in contact with a top surface of the bottom spacer, wherein the encapsulation layer is in contact with the top surface of the bottom spacer;
• a bottom source/drain contact to the bottom source/drain region;
• and
• a gate contact to the gate stack, wherein the bottom source drain contact and the gate contact each comprises a single solid structure with a top portion having a width W1CONTACT over a bottom portion having a width W2CONTACT, wherein W2CONTACT<W1CONTACT, and wherein the bottom portion having the width W2CONTACT is present alongside the gate stack and the top source/drain region.

A method of forming a vertical transport field effect transistor (VTFET) device, the method comprising:

• forming a VTFET comprising:
• at least one fin serving as a vertical fin channel, a bottom source/drain region present at a base of the at least one fin, a bottom spacer is located over the bottom source/drain region, a gate stack alongside the at least one fin, an encapsulation layer disposed over the gate stack, and a top source/drain region present at a top of the at least one fin, wherein the gate stack extends along a vertical sidewall of the at least one fin, wherein the encapsulation layer in in contact with a sidewall of the top source/drain region and a vertical sidewall of the gate stack, wherein the bottom spacer is located adjacent to the sidewalls of the at least one fin, wherein the gate stack is in contact with a top surface of the bottom spacer, wherein the encapsulation layer is in contact with the top surface of the bottom spacer;
• depositing a first ILD over the VTFET;
• depositing a capping layer on the first ILD;
• depositing a second ILD on the capping layer;
• forming contact trenches in the second ILD, wherein the contact trenches comprise at least a first contact trench over the bottom source/drain region and a second contact trench over the gate stack;
• forming sidewall spacers along sidewalls of the contact trenches;
• performing an etch between the sidewall spacers to extend the contact trenches through the capping layer and the first ILD;
• removing the sidewall spacers such that each of the contact trenches comprises a top portion having a width W1TRENCH over a bottom portion having a width W2TRENCH, wherein W2TRENCH<W1TRENCH, and wherein a sidewall along the top portion is discontinuous with a sidewall along the bottom portion;
• and
• filling the top portion and the bottom portion of each of the contact trenches with at least one contact metal to form a single solid structure therein.