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US 12,191,387 B2Granted
High voltage semiconductor device and manufacturing method thereof
AssigneeSK keyfoundry Inc.
InventorHanseob Cha
Life of this patent
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Abstract
A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes: a first conductive type buried layer disposed on a substrate; a first conductive type deep well region, a second conductive type body region, and a first conductive type drift region which are disposed on the first conductive type buried layer; a source region disposed in the second conductive type body region; a drain region disposed in the first conductive type deep well region; and a gate electrode disposed on the second conductive type body region and the first conductive type drift region.
Claims19
A semiconductor device, comprising:
- a first conductive type buried layer disposed on a substrate;
- a first conductive type deep well region, a second conductive type body region, and a first conductive type drift region which are disposed on the first conductive type buried layer, wherein the first conductive type buried layer has a doping concentration greater than that of the first conductive type deep well region;
- a source region disposed in the second conductive type body region;
- a drain region disposed in the first conductive type deep well region;
- a gate electrode disposed on the second conductive type body region and the first conductive type drift region;
- a shallow trench isolation region disposed below the gate electrode;
- and
- a deep trench isolation region disposed adjacent to the drain region,
- wherein the source region is disposed between two adjacent gate electrodes and spaced apart from the deep trench isolation region,
- wherein the first conductive type buried layer comprises:
- a first region disposed on the substrate;
- and
- a second region disposed on either edge of the first region, and
- wherein a top surface of the second region is formed higher than a top surface of the first region with respect to a bottom surface of the first conductive type buried layer.
11 more elements
A semiconductor device manufacturing method, the method comprising:
- providing a substrate;
- forming a shallow trench isolation region in the substrate;
- forming a first conductive type buried layer in the substrate;
- forming a first conductive type deep well region, a second conductive type body region, and a first conductive type drift region on the first conductive type buried layer, wherein the first conductive type buried layer has a doping concentration greater than that of the first conductive type deep well region;
- forming a gate electrode on the second conductive type body region and the first conductive type drift region;
- forming a source region in the second conductive type body region;
- forming a drain region on the first conductive type deep well region;
- and
- forming a deep trench isolation region adjacent to the drain region, wherein the source region is formed between two adjacent gate electrodes and spaced apart from the deep trench isolation region,
- wherein the forming a first conductive type buried layer comprises:
- forming a first region by implanting a first conductive type impurity into a top surface of the substrate;
- and
- forming a second region on either edge of the first region by further implanting the first conductive type impurity into the first region,
- wherein a top surface of the second region is formed higher than a top surface of the first region with respect to a bottom surface of the first conductive type buried layer, and
- wherein the second region overlaps vertically with the first conductive type deep well region.
12 more elements
A semiconductor device, comprising:
- a substrate;
- a first layer doped with a high concentration N-type impurity and disposed on the substrate;
- a second layer doped with a high concentration P-type impurity and disposed on the first layer;
- a third layer doped with the high concentration P-type impurity and disposed on the first layer;
- a conductive type body region disposed on a side of the second layer, wherein each of the second layer and the third layer is in direct contact with the conductive type body region;
- a conductive type drift region disposed on the second layer;
- a conductive type deep well region disposed on the first layer;
- a shallow trench isolation region disposed on the conductive type deep well region;
- a gate electrode arranged to overlap the conductive type body region, the conductive type drift region, and the shallow trench isolation region;
- a drain region disposed adjacent to the shallow trench region;
- a source region disposed between two adjacent gate electrodes;
- and
- a deep trench isolation region disposed adjacent to the drain region,
- wherein the source region is spaced apart from the deep trench isolation region.
11 more elements
Dependencies are inferred from the claim text.