High electron mobility transistor with source and drain electrodes below the channel

A semiconductor transistor structure, comprising:

• a source electrode;
• a drain electrode on a same plane as the source electrode;
• a channel region on top of the source and drain electrodes and configured to carry a current;
• a gate structure comprising a metallic material on top of the channel region;
• a substrate configured as a chip carrier;
• and
• an oxide layer on top of the chip carrier substrate, wherein:
• the source and drain electrodes are located on a side that is opposite to that of the gate structure, with respect to the channel region;
• the source and drain electrodes are on top of the chip carrier substrate;
• and
• the source and drain electrodes are on a left and a right side of the oxide layer, respectively.

A method of fabricating a semiconductor transistor structure, comprising:

• providing a first substrate;
• providing a first buffer layer on top of the first substrate;
• providing a gate barrier layer on top of the first buffer layer;
• providing a quantum well channel layer on top of the gate barrier layer;
• providing a second buffer layer on top of the quantum well channel layer;
• providing a contact layer on top of the second buffer layer;
• providing a first photoresist layer having a pattern, on top of the contact layer, to define an etch gate recess region;
• removing a center portion of the contact layer below the photoresist pattern, thereby defining a source and a drain on the contact layer;
• removing the first photoresist;
• depositing an electrode on the drain contact and an electrode on the source contact;
• depositing an oxide layer on top of the source and drain electrodes, and the buffer layer;
• planarizing the oxide layer;
• flipping the transistor structure and direct bonding to a carrier substrate;
• removing the first substrate, thereby exposing the first buffer layer;
• providing a second photoresist layer having a pattern on top of the exposed first buffer layer;
• depositing a metal gate structure on top of the exposed first buffer layer;
• and
• configuring the gate structure to have a T shape.