Multi-gate semiconductor device with inner spacer and fabrication method thereof

A method of manufacturing a semiconductor device, comprising:

• forming a stack of first type and second type epitaxial layers on a semiconductor substrate, the first type and second type epitaxial layers having different material compositions and being alternatingly disposed in a vertical direction;
• patterning the stack to form a fin structure;
• forming a sacrificial gate structure over the fin structure;
• removing at least the first type epitaxial layers from a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure;
• forming an insulating layer on lateral ends of the first type epitaxial layers;
• forming an S/D epitaxial feature in contact with the insulating layer and the second type epitaxial layers, wherein the insulating layer interposes the S/D epitaxial feature and the first type epitaxial layers, and wherein the S/D epitaxial feature traps air gaps laterally between the S/D epitaxial feature and the insulating layer;
• removing the sacrificial gate structure and the first type epitaxial layers, resulting in a gate trench;
• and
• partially etching a portion of the insulating layer exposed in the gate trench.

A method of manufacturing a semiconductor device, comprising:

• forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked, the first and second semiconductor layers having different material compositions;
• forming a sacrificial gate structure over the fin structure;
• forming a gate spacer on sidewalls of the sacrificial gate structure;
• etching a region of the fin structure not covered by the sacrificial gate structure and the gate spacer, thereby forming a trench;
• laterally etching the first semiconductor layers through the trench, thereby forming recesses;
• depositing an insulating layer on surfaces of the first and second semiconductor layers exposed in the recesses;
• growing an epitaxial feature in the trench, thereby trapping at least an air gap in one of the recesses;
• removing the sacrificial gate structure, thereby forming a gate trench;
• removing the first semiconductor layers from the gate trench to expose a first portion of the insulating layer in the gate trench;
• and
• forming a metal gate stack in the gate trench and in contact with the first portion of the insulating layer,
• wherein the insulating layer includes a second portion in contact with the epitaxial feature, and a thickness of the second portion is larger than a thickness of the first portion.