Source and drain engineering process for multigate devices

A method, comprising:

• forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition;
• patterning the semiconductor stack to form a semiconductor fin;
• forming an isolation feature over the substrate to surround a bottom portion of the semiconductor fin;
• after the forming of the isolation feature, depositing a semiconductor cladding layer along a top surface and sidewalls of the semiconductor fin;
• after the depositing of the semiconductor cladding layer, forming a dielectric fin over a top surface of the isolation feature next to the semiconductor fin;
• forming a first gate stack on the semiconductor fin and the dielectric fin;
• after the forming of the first gate stack, selectively removing the semiconductor cladding layer;
• etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess;
• and
• epitaxially growing a source/drain feature in the source/drain recess in a cyclic process, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin, wherein each cycle of the cyclic process includes a first duration of deposition using a first precursor having a deposition chemical and a second duration of etching using a second precursor having an etching chemical.

A method, comprising:

• forming a semiconductor stack on a substrate, wherein the semiconductor stack includes a first semiconductor layers and a second semiconductor layers alternatively disposed, the first semiconductor layers and the second semiconductor layers being different in composition;
• patterning the semiconductor stack to form a semiconductor fin;
• forming an isolation feature over the substrate to surround a bottom portion of the semiconductor fin;
• after the forming of the isolation feature, depositing a semiconductor cladding layer along a top surface and sidewalls of the semiconductor fin;
• after the depositing of the semiconductor cladding layer, forming a dielectric fin over a top surface of the isolation feature next to the semiconductor fin;
• forming a first gate stack on the semiconductor fin and the dielectric fin;
• after the forming of the first gate stack, selectively removing the semiconductor cladding layer;
• etching to a portion of the semiconductor fin within a source/drain region, resulting in a source/drain recess;
• and
• epitaxially growing a source/drain feature in the source/drain recess in a cyclic process, defining an airgap spanning between a sidewall of the source/drain feature and a sidewall of the dielectric fin, wherein each cycle of the cyclic process includes a first duration of deposition using a first precursor having a silicon-containing deposition chemical and a second duration of etching using a second precursor having a chlorine-containing etching chemical.