Field effect transistor with a negative capacitance gate structure

A method for operating a field effect transistor with a negative capacitance gate structure, wherein the field effect transistor comprises a channel and a gate dielectric arranged over the channel, wherein the negative capacitance gate structure comprises:

• a bottom electrode structure comprising a bottom electrode, wherein at least a section of the bottom electrode structure is arranged over the gate dielectric,
• a multi-domain structure comprising a multi-domain element arranged over the bottom electrode, the multi-domain element comprising a plurality of topological domains and at least one topological domain wall, and
• a top electrode structure comprising a top electrode arranged over the multi- domain element,
• wherein the multi-domain element comprises:
• a cross-sectional area with an orientation corresponding to an orientation of a top surface of the bottom electrode, the cross-sectional area defining a shortest separation line to divide the cross sectional-area into a plurality of regions of essentially equal area,
• a reference line shifted with respect to the shortest separation line and in a surface defined by the cross-sectional area, and
• wherein a length of the reference line within the cross-sectional area is shorter than a length of the shortest separation line within the cross-sectional area by a difference which increases with increasing distance between the reference line and the shortest separation line in a vicinity of the shortest separation line;
• the method comprising:
• increasing a voltage of the top electrode by its modulus to reach a gate voltage, thereby changing a shape of the topological domain wall and causing an amplified voltage of the bottom electrode with a modulus larger than a modulus of the gate voltage.