Image sensor having a gate dielectric structure for improved device scaling

An image sensor comprising:

• an isolation structure disposed in a semiconductor substrate, wherein the isolation structure extends vertically through the semiconductor substrate from a first surface of the semiconductor substrate to a second surface of the semiconductor substrate opposite the first surface of the semiconductor substrate;
• a floating diffusion node disposed in the semiconductor substrate and on a side of the isolation structure;
• a photodetector disposed in the semiconductor substrate and laterally between the floating diffusion node and the isolation structure;
• a gate electrode structure disposed over the semiconductor substrate and laterally between the floating diffusion node and the photodetector, wherein the first surface of the semiconductor substrate is disposed vertically between the gate electrode structure and the second surface of the semiconductor substrate;
• a first gate dielectric structure disposed over the first surface of the semiconductor substrate;
• and
• a second gate dielectric structure disposed over the first surface of the semiconductor substrate and on a side of the first gate dielectric structure, wherein a thickness of the second gate dielectric structure is greater than a thickness of the first gate dielectric structure, wherein the second gate dielectric structure overlies the isolation structure, and wherein the gate electrode structure partially overlies both the first gate dielectric structure and the second gate dielectric structure.

A method for forming an image sensor, the method comprising:

• forming a photodetector in a semiconductor substrate;
• forming a first gate dielectric structure over a first side of the semiconductor substrate;
• forming a second gate dielectric structure over the first side of the semiconductor substrate, wherein the second gate dielectric structure is formed with a thickness that is greater than a thickness of the first gate dielectric structure;
• forming a gate electrode structure partially over the first gate dielectric structure and partially over the second gate dielectric structure;
• forming a trench in the semiconductor substrate that exposes a portion of the second gate dielectric structure, wherein the trench is formed from a second side of the semiconductor substrate opposite the first side of the semiconductor substrate;
• and
• forming a back-side deep trench isolation (BDTI) structure in the trench.