Multi-gate device and related methods

A semiconductor device, comprising:

• a first fin in a first region of a substrate and a second fin in a second region of the substrate, wherein the first fin includes a first plurality of a first type of epitaxial layers having a first material composition, and wherein the second fin includes a second plurality of a second type of epitaxial layers having a second material composition different than the first material composition;
• a first portion of a first gate structure disposed between adjacent epitaxial layers of the first type of epitaxial layers in a first channel region of the first fin, wherein one of the adjacent layers of the first type of epitaxial layers is a topmost epitaxial layer in the first channel region of the first fin, and wherein the first portion of the first gate structure includes a gate dielectric layer that fills an entirety of a space between the adjacent epitaxial layers of the first type of epitaxial layers;
• a second portion of the first gate structure disposed over the first portion of the first gate structure and over the topmost epitaxial layer in the first channel region;
• and
• a first epitaxial source/drain, wherein a first lateral end of the first portion of the first gate structure includes the gate dielectric layer that is both in contact with the first epitaxial source/drain and free of contact with each spacer layer of the semiconductor device, and wherein the second portion of the first gate structure includes the gate dielectric layer in contact with both a top surface of the topmost epitaxial layer in the first channel region and with the first epitaxial source/drain.

A multi-gate semiconductor device, comprising:

• a first fin element including a plurality of silicon epitaxial layers;
• a first gate structure over a channel region of the first fin element, wherein a first portion of the first gate structure is disposed between first and second layers of the plurality of silicon epitaxial layers, wherein the first portion of the first gate structure includes a gate dielectric layer that fills an entirety of a space between the first and second layers of the plurality of silicon epitaxial layers, and wherein a second portion of the first gate structure is disposed over a topmost layer of the plurality of silicon epitaxial layers;
• a spacer disposed on a sidewall of the first gate structure;
• and
• a first epitaxial source/drain feature adjacent to the channel region of the first fin element;
• wherein the first epitaxial source/drain feature abuts the gate dielectric layer of the first and second portions of the first gate structure, wherein the first portion of the first gate structure extends beneath the spacer, and wherein the gate dielectric layer of the second portion of the first gate structure extends beneath the spacer.