Integrated circuit

A method, comprising:

• forming first to second active regions, that are of a first conductivity type, coupled between a pad and a first voltage terminal, wherein the first to second active regions have different widths;
• forming a first gate interposed between the first to second active regions to form a first transistor;
• forming third to fourth active regions, that are of the first conductivity type, coupled between the pad and the first voltage terminal;
• forming a second gate interposed between the third to fourth active regions to form a second transistor;
• and
• forming a first conductive segment that is coupled to the first and third active regions and configured to transmit an electrostatic discharge (ESD) current from the pad to the first active region and to the third active region.

An integrated circuit, comprising:

• a first transistor comprises a first active region coupled between a first voltage terminal and a pad;
• a second transistor comprising a second active region coupled between the pad and the first voltage terminal, wherein the first and second transistors are configured to discharge a first electrostatic discharge (ESD) current;
• and
• a third transistor comprising a third active region coupled between the pad and a second voltage terminal different from the first voltage terminal, and configured to discharge a second electrostatic discharge current,
• wherein a width of the third active region is smaller than that of the first and second active region.