Facilitating alignment of stacked chiplets

A method for designing a semiconductor device, the method comprising:

• generating a two-dimensional design for fabricating a plurality of chiplets on a semiconductor substrate of a semiconductor wafer, the plurality of chiplets being component levels for a multi-chip integrated circuit, the two-dimensional design comprising:
• a first layout for alignment features and semiconductor structures to be formed on a first surface of a first chiplet of the plurality of chiplets;
• a second layout for alignment features and semiconductor structures to be formed on a first surface of a second chiplet of the plurality of chiplets, the second chiplet being adjacent to the first chiplet on the semiconductor substrate of the semiconductor wafer, the second layout being a mirror image of the first layout across a reference line shared by the first chiplet and the second chiplet, the first surface of the first chiplet and the first surface of the second chiplet both being either top surfaces or bottom surfaces;
• and
• generating one or more photomasks according to the design.

A method for designing a semiconductor device, the method comprising:

• generating a two-dimensional design for fabricating a plurality of chiplets on a semiconductor substrate, the plurality of chiplets being component levels for a multi-chip integrated circuit, the two-dimensional design comprising:
• a first layout for alignment features and semiconductor structures to be formed on a first surface of a first chiplet of the plurality of chiplets;
• a second layout for alignment features and semiconductor structures to be formed on a first surface of a second chiplet of the plurality of chiplets, the second chiplet being adjacent to the first chiplet on the semiconductor substrate, the second layout being a mirror image of the first layout across a reference line shared by the first chiplet and the second chiplet, the first surface of the first chiplet and the first surface of the second chiplet both being either top surfaces or bottom surfaces;
• a third layout for alignment features and semiconductor structures to be formed on a second surface of the first chiplet;
• and
• a fourth layout for alignment features and semiconductor structures to be formed on a first surface of a third chiplet of the plurality of chiplets, the third chiplet being adjacent to the first chiplet on the semiconductor substrate, the fourth layout being a mirror image of the third layout across a reference line shared by the first chiplet and the third chiplet, the second surface of the first chiplet and the first surface of the third chiplet both being either top surfaces or bottom surfaces;
• and
• generating one or more photomasks according to the design.