Integrated voltage regulator (IVR) package including inductor and capacitor and IVR system package including the IVR package

An integrated voltage regulator (IVR) system package comprising:

• an IVR package;
• and
• a memory package including a memory chip and stacked on the IVR package,
• wherein the IVR package comprises:
• a lower package substrate;
• a stacked structure mounted on the lower package substrate and having a stack structure in which a passive device chip including one or more capacitors and an IVR chip including a voltage regulator are stacked;
• and
• an intermediate substrate disposed on the lower package substrate in a structure surrounding the stacked structure, and including vias therein, and
• wherein one or more inductors are included in the stacked structure or the intermediate substrate.

A 3-dimensional (3D) package having a package on package (POP) structure, the 3D package comprising:

• a lower package substrate;
• a passive device chip mounted on the lower package substrate and comprising one or more capacitors;
• a lower chip mounted on the lower package substrate and disposed adjacent to the passive device chip;
• an integrated voltage regulator (IVR) chip disposed commonly over the passive device chip and the lower chip, and including a voltage regulator;
• an intermediate substrate disposed on the lower package substrate in a structure surrounding the passive device chip, the lower chip, and the IVR chip, the intermediate substrate including vias therein;
• an inner sealing material configured to fill a space between the passive device chip, the lower chip, and the IVR chip and the intermediate substrate and sealing the passive device chip, the lower chip, and the IVR chip;
• and
• a memory package mounted on the intermediate substrate, and including a memory chip,
• wherein one or more inductors are arranged in the intermediate substrate by using the vias.