Shared pad/bridge layout for a 3D IC

A three-dimensional (3D) integrated circuit (IC) comprising:

• a plurality of pads arranged in a row and comprising a first-die pad, a second-die pad, and a third-die pad;
• a first IC die underlying the plurality of pads, and comprising a first-die semiconductor device electrically coupled to the first-die pad by a first-die conductive path;
• a second IC die underlying the first IC die, and comprising a second-die semiconductor device electrically coupled to the second-die pad by a second-die conductive path;
• a third IC die underlying the second IC die, and comprising a third-die semiconductor device electrically coupled to the third-die pad by a third-die conductive path;
• and
• a plurality of via layers and a plurality of metal layers alternatingly stacked across the first, second, and third IC dies and forming a second-die pad/bridge structure and a third-die pad/bridge structure respectively at the second and third IC dies, wherein the second-die and third-die pad/bridge structures are the same and each comprises a plurality of bridge wires at a common elevation and having greatest dimensions extending in parallel from directly under the second-die pad to directly under the third-die pad, and wherein the second-die and third-die conductive paths extend along individual bridge wires of the second-die pad/bridge structure.

A method for forming a three-dimensional (3D) integrated circuit (IC), the method comprising:

• forming a first IC die, a second IC die, and a third IC die;
• bonding the second IC die to the first and third IC dies, such that the second IC die is between the first and third IC dies;
• and
• forming a plurality of backside pads arranged in a first row and overlying the first, second, and third IC dies, wherein the plurality of backside pads comprises a first-die backside pad, a second-die backside pad, and a third-die backside pad electrically coupled respectively to individual semiconductor devices of the first, second, and third IC dies;
• wherein the second and third IC dies each comprises an alternating stack of via layers and metal layers, including a top metal (TM) layer and a TM-1 layer, wherein the TM layer comprises a plurality of TM pads arranged in a second row, and wherein the TM-1 layer comprises a plurality of bridge wires elongated in parallel from directly under a TM pad of the plurality of TM pads to directly under another TM pad of the plurality of TM pads;
• wherein the backside pads are formed respectively overlying the TM pads of the second IC die and the TM pads of the third IC die, and wherein the second-die and third-die backside pads are electrically coupled respectively to the individual semiconductor devices of the second and third IC dies respectively through the bridge wires of the second IC die;
• and
• wherein the TM and TM-1 layers of the second IC die are formed using the same photoreticles/photomasks respectively as the TM and TM-1 layers of the third IC die.