Integrated circuit package and method of forming same

A method comprising:

• forming active devices along a front-side of a first substrate, the first substrate comprising a through via extending from the front-side partially through the first substrate;
• forming a first interconnect structure over the active devices and the front-side of the first substrate, forming the first interconnect structure comprising:
• forming a first conductive line layer over the active devices;
• forming a second conductive line layer and first memory elements over the first conductive line layer;
• and
• forming a third conductive line layer over the second conductive line layer and the first memory elements;
• attaching a second substrate over the third conductive line layer;
• thinning a back-side of the first substrate to expose the through via;
• and
• forming a second interconnect structure over the through via and the back-side of the first substrate, the second interconnect structure comprising second memory elements.

A method comprising:

• forming a first memory array over a front-side of a first substrate, forming the first memory array comprising:
• forming first transistors along the front-side of the first substrate;
• forming a first portion of a first interconnect structure over the first transistors;
• and
• forming first memory elements over the first portion of the first interconnect structure;
• forming a second portion of the first interconnect structure over the first memory elements;
• forming a second memory array over a back-side of the first substrate, forming the second memory array comprising:
• simultaneously with forming the first transistors, forming second transistors along the front-side of the first substrate;
• thinning the back-side of the first substrate to expose through vias embedded in the first substrate;
• forming a first portion of a second interconnect structure over the through vias and the back-side of the first substrate;
• and
• forming second memory elements over the first portion of the second interconnect structure;
• and
• forming a second portion of the second interconnect structure over the second memory elements.