Semiconductor device having integral alignment marks with decoupling features and method for fabricating the same
AssigneeNanya Technology Corporation
InventorShing-Yih Shih
Life of this patent
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Abstract
The present application discloses a semiconductor device having integral alignment marks with decoupling features and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a dielectric stack positioned on the substrate; two conductive features positioned in the dielectric stack; a decoupling unit positioned in the dielectric stack, between the two second conductive features, and comprising a bottle-shaped cross-sectional profile; and an alignment mark positioned on the decoupling unit. The alignment mark comprises a fluorescence material.
Claims12
A semiconductor device, comprising:
- a substrate;
- a dielectric stack positioned on the substrate;
- two second conductive features positioned in the dielectric stack;
- a decoupling unit positioned in the dielectric stack, between the two second conductive features, wherein the decoupling unit has low dielectric constant for providing decoupling function and for reducing parasitic capacitance of the second conductive features;
- and
- an alignment mark positioned on the decoupling unit;
- wherein the alignment mark comprises a fluorescent material;
- wherein the fluorescent material comprises azobenzene;
- wherein the decoupling unit comprises a porous low-k material;
- wherein the dielectric stack comprises a first dielectric layer positioned on the substrate, a second dielectric layer positioned on the first dielectric layer, a middle dielectric layer positioned on the second dielectric layer, a third dielectric layer positioned on the middle dielectric layer, and a fourth dielectric layer positioned on the third dielectric layer, and the two second conductive features and the decoupling unit are positioned in the middle dielectric layer.
Dependencies are inferred from the claim text.