Electronic devices including tiered stacks including conductive structures isolated by slot structures, and related systems and methods

A method of forming an electronic device, the method comprising:

• forming a first stack comprising alternating first materials and second materials over a source tier;
• forming strings of memory cells comprising a channel material extending vertically through the first stack;
• forming a second stack comprising alternating additional first materials and additional second materials over the first stack;
• forming pillars comprising an additional channel material extending through the second stack and over some of the strings of memory cells, a center of each of the pillars horizontally offset in a first horizontal direction and in a second horizontal direction transverse to the first horizontal direction from a center of a corresponding string of memory cells;
• forming conductive lines over the pillars;
• and
• forming interconnect structures directly contacting the pillars and the conductive lines.

An electronic device, comprising:

• strings of memory cells extending through a first stack comprising tiers of alternating first conductive structures and first insulative structures, the strings of memory cells comprising at least a dielectric material and a channel material extending vertically through the first stack;
• a second stack comprising tiers of alternating second conductive structures and second insulative structures overlying the first stack;
• conductive lines overlying the second stack and extending in a horizontal direction;
• a first pillar extending through the second stack and overlying a first of the strings of memory cells, the first pillar horizontally offset from a center of the first of the strings of memory cells at a first acute angle to the horizontal direction;
• a second pillar extending through the second stack and vertically overlying a second of the strings of memory cells, the second pillar horizontally offset from a center of the second of the strings of memory cells at a second acute angle from the horizontal direction, one or more of the first pillar and the second pillar comprising a lower portion laterally adjacent to the second conductive structures of the second stack and an upper portion located above an uppermost second conductive structure;
• and
• the second conductive structures comprising upper select gates separated from the first conductive structures by an interdeck region, the lower portion of the first pillar and the second pillar laterally adjacent to the upper select gates, and the upper portion of the first pillar and the second pillar located above an uppermost upper select gate.

A system, comprising:

• a processor operably coupled to an input device and an output device;
• and
• electronic devices operably coupled to the processor, the one or more of the electronic devices comprising:
• vertically extending strings of memory cells coupled to access line structures and at least one source structure;
• pillars overlying and coupled to the vertically extending strings of memory cells, each of the pillars comprising:
• an insulative material;
• and
• a channel material substantially laterally surrounding the insulative material;
• elliptical conductive structures overlying and coupled directly to the channel material of the pillars;
• and
• digit line structures overlying and coupled directly to the elliptical conductive structures.