Method of forming bottom electrode via for memory device

A method, comprising:

• forming a lower insulating structure over a lower dielectric structure surrounding one or more lower interconnects;
• forming a bottom electrode via opening to extend through the lower insulating structure and expose the one or more lower interconnects;
• forming a barrier layer within the bottom electrode via opening;
• forming a glue layer over the barrier layer;
• forming a conductive core over the glue layer;
• forming a memory device stack over the conductive core, the glue layer, and the barrier layer;
• and
• patterning the memory device stack and the barrier layer to form a memory device over a barrier and the glue layer, wherein the barrier comprises a sidewall disposed along an interior sidewall of the lower insulating structure and a horizontally extending segment protruding outward from the sidewall to above a top surface of the lower insulating structure, after the patterning is complete.

A method, comprising:

• forming one or more interconnects within an inter-level dielectric (ILD) structure;
• patterning an upper surface of the ILD structure to form a bottom electrode via opening exposing the one or more interconnects;
• forming a barrier layer within the bottom electrode via opening and over the ILD structure;
• forming a conductive core material over the barrier layer;
• performing a mechanical polishing process to remove a first part of the conductive core material and expose an upper surface of the barrier layer, wherein the upper surface of the barrier layer is directly over the upper surface of the ILD structure after the mechanical polishing process;
• performing a buffing process to remove a second part of the conductive core material and to form a conductive core;
• and
• forming a memory device over the conductive core.