Chip-on-film package having redistribution pattern between semiconductor chip and connection terminal

A chip-on-film package, comprising:

• a film substrate including a chip region and an edge region;
• a plurality of lead lines on a top surface of the edge region of the film substrate;
• a semiconductor chip on a top surface of the chip region of the film substrate, the semiconductor chip comprising a row of chip pads, the row of chip pads including at least a first chip pad, and a second chip pad, and at least two third chip pads spaced apart from each other in a first horizontal direction such that the first chip pad and the second chip pad are between the third chip pads in the first horizontal direction and such that the row of chip pads is spaced apart from the third chip pads in a second horizontal direction;
• a plurality of redistribution patterns on a bottom surface of the semiconductor chip, the plurality of redistribution patterns comprising first, second and third redistribution patterns;
• and
• a plurality of terminals connecting the first and second redistribution patterns to the plurality of lead lines,
• wherein the first chip pad and the first redistribution pattern are vertically overlap with a first lead line of the plurality of lead lines, and the first redistribution pattern electrically connects the first chip pad and the first lead line,
• the second chip pad is spaced apart from a second lead line of the plurality of lead lines, and the second redistribution pattern electrically connects the second chip pad and second first lead line, and
• the third redistribution pattern connects the third chip pads across a space corresponding to a center region of the semiconductor chip, when viewed in a plan view, and a third lead line of the plurality of lead lines across the center region and connect the third redistribution pattern, and
• wherein the first horizontal direction and the second horizontal direction are different from each other.

A chip-on-film package, comprising:

• a film substrate including a chip region and an edge region;
• a plurality of lead lines on a top surface of the edge region of the film substrate, the lead lines comprising first and second lead lines;
• a semiconductor chip on a top surface of the chip region of the film substrate, the semiconductor chip comprising a row of chip pads, the row of chip pads including at least a first chip pad and a second chip pad, and at least two third chip pads spaced apart from each other in a first horizontal direction such that the first chip pad and the second chip pad are between the third chip pads in the first horizontal direction and such that the row of chip pads is spaced apart from the third chip pads in a second horizontal direction;
• a plurality of redistribution patterns on a bottom surface of the semiconductor chip, the plurality of redistribution patterns comprising first, and second, and third redistribution patterns;
• a first terminal connecting the first redistribution pattern and the first lead line;
• and
• a second terminal connecting the second redistribution pattern and the second lead line,
• wherein the first chip pad, the first redistribution pattern and the first terminal are vertically aligned, and the first redistribution pattern electrically connects the first chip pad and the first lead line,
• the third redistribution pattern connects the third chip pads across a space corresponding to a center region of the semiconductor chip in the first direction, when viewed in a plan view,
• the second redistribution pattern horizontally extends in the second direction, which is acrosses the first direction, and connected to the third redistribution pattern.