Semiconductor package

A semiconductor package comprising:

• a base substrate comprising a first interconnection structure;
• an interposer substrate comprising a semiconductor substrate having a first surface facing the base substrate and a second surface opposing the first surface, an interconnection region on the second surface and comprising a second interconnection structure, a plurality of through-vias extending through the semiconductor substrate and electrically connecting the second interconnection structure to the first interconnection structure, and a passivation layer on at least a portion of the first surface;
• a plurality of connection bumps between the base substrate and the interposer substrate and electrically connecting the plurality of through-vias to the first interconnection structure;
• a plurality of dummy patterns on the first surface of the interposer substrate, and embedded in the passivation layer;
• an underfill resin in a space between the base substrate and the interposer substrate;
• and
• first and second semiconductor chips on the interconnection region of the interposer substrate and electrically connected to each other by the second interconnection structure,
• wherein the interposer substrate comprises a first region comprising the plurality of through-vias, a second region adjacent a periphery of the first region, and a third region adjacent a periphery of the second region,
• the first region and the second region include the passivation layer thereon, and
• the third region is free of the passivation layer.

A semiconductor package comprising:

• an interposer substrate having a first surface, a second surface opposing the first surface, and a side surface between the first surface and the second surface;
• a passivation layer on a portion of the first surface of the interposer substrate;
• first and second semiconductor chips on a second surface of the interposer substrate opposite the first surface, and electrically connected to each other through the interposer substrate;
• and
• an underfill resin in contact with at least a portion of the first surface of the interposer substrate that is exposed by the passivation layer, and at least a portion of the side surface of the interposer substrate.