Semiconductor package

A semiconductor package, comprising:

• a redistribution substrate comprising a first surface and a second surface, which are opposite to each other;
• a first semiconductor chip and a second semiconductor chip on the first surface of the redistribution substrate,
• each of the first semiconductor chip and the second semiconductor chip comprising an active surface and an inactive surface, which are opposite each other;
• a third semiconductor chip between the first semiconductor chip and the redistribution substrate and between the second semiconductor chip and the redistribution substrate;
• a first molding portion on a side surface of each of the first semiconductor chip and the second semiconductor chip;
• a second molding portion between the redistribution substrate and the first molding portion, the second molding portion on a side surface of the third semiconductor chip;
• and
• a mold via penetrating the second molding portion and electrically connecting the redistribution substrate to the first semiconductor chip,
• wherein a width of the mold via in the second molding portion increases in a direction from the first semiconductor chip toward the redistribution substrate, and
• the first molding portion is in contact with the inactive surface of each of the first semiconductor chip and the second semiconductor chip.

A semiconductor package, comprising:

• a redistribution substrate comprising a first surface and a second surface, which are opposite each other, wherein
• the redistribution substrate includes an insulating layer, a first redistribution pattern in the insulating layer, a second redistribution pattern in the insulating layer, a third redistribution pattern in the insulating layer, and a bonding pad on the third redistribution pattern, and
• the first redistribution pattern, the second redistribution pattern, and the third redistribution pattern are sequentially stacked in a direction from the first surface of the redistribution substrate toward the second surface;
• a first semiconductor chip and a second semiconductor chip on the first surface of the redistribution substrate,
• each of the first semiconductor chip and the second semiconductor chip comprising an active surface and an inactive surface, which are opposite to each other;
• a first chip pad adjacent to the active surface of the first semiconductor chip;
• a second chip pad adjacent to the active surface of the second semiconductor chip;
• a first molding portion on a side surface and the inactive surface of each of the first semiconductor chip and the second semiconductor chip;
• a third semiconductor chip between the first semiconductor chip and the redistribution substrate and between the second semiconductor chip and the redistribution substrate;
• an adhesive layer between the first semiconductor chip and the third semiconductor chip and between the second semiconductor chip and the third semiconductor chip;
• a second molding portion between the redistribution substrate and the first molding portion, the second molding portion being provided on a side surface of the third semiconductor chip and a top surface of the third semiconductor chip;
• bump patterns between the redistribution substrate and the third semiconductor chip;
• a mold via penetrating the second molding portion and electrically connecting the redistribution substrate to the first semiconductor chip;
• and
• a connection terminal provided on the bonding pad, wherein
• the mold via is in contact with the second redistribution pattern, and
• the bump patterns are in contact with the first redistribution pattern.