US 12,191,211 B2 · Method for making semiconductor device using a stress memorization technique

Abstract

A method for fabricating a semiconductor device is disclosed. A substrate having thereon at least one metal-oxide-semiconductor (MOS) transistor is provided. A stress memorization technique (SMT) process is performed. The SMT process includes steps of depositing an SMT film covering the at least one MOS transistor on the substrate, and subjecting the SMT film to a thermal process. A lithographic process and an etching process are performed to form a patterned SMT film. A silicide layer is formed on the MOS transistor. The patterned SMT film acts as a salicide block layer when forming the silicide layer.

Claims7

Dependent claims

A method for fabricating a semiconductor device, comprising:

providing a substrate having thereon at least one metal-oxide-semiconductor (MOS) transistor;
performing a stress memorization technique (SMT) process comprising depositing an SMT film covering the at least one MOS transistor on the substrate, and subjecting the SMT film to a thermal process;
after the SMT process, performing a lithographic process and an etching process to form a patterned SMT film;
and
forming a silicide layer on the MOS transistor, wherein the patterned SMT film acts as a salicide block layer when forming the silicide layer.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/752,869Filed 25 May 2022

Priority

CN 202210472495.229 Apr 2022

Published

US 2023/0352347 A12 Nov 2023

Granted

7 Jan 2025

Term ends

Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10D 30/796
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: having memorised stress for introducing strain in the…
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 30/0212
Of FETs having insulated gates [IGFET]: using self-aligned silicidation
H10D 30/601
Insulated-gate field-effect transistors [IGFET]: having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs

Method for making semiconductor device using a stress memorization technique

Life of this patent

Method for making semiconductor device using a stress memorization technique

Life of this patent

Abstract

Claims7