Semiconductor devices including semiconductor pattern

A semiconductor device comprising:

• a plurality of semiconductor patterns disposed on a substrate, each of the plurality of semiconductor patterns extending longitudinally in a first horizontal direction that is parallel to an upper surface of the substrate, each of the plurality of semiconductor patterns including:
• a first semiconductor pattern having first-conductivity-type impurities, a second semiconductor pattern having second-conductivity-type impurities that are different from the first-conductivity-type impurities, and a third semiconductor pattern disposed between the first semiconductor pattern and the second semiconductor pattern, wherein the first to third semiconductor patterns are contiguously arranged in the first horizontal direction,
• the third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern, wherein at least one of the first region and the second region comprises an intrinsic semiconductor layer;
• a plurality of first conductive lines extending in a second horizontal direction parallel to the upper surface of the substrate and crossing the first horizontal direction, the plurality of first conductive lines is spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate;
• a plurality of second conductive lines spaced apart from the first conductive line in the first horizontal direction, extending longitudinally in the vertical direction and spaced apart from each other in the second horizontal direction, each of the plurality of second conductive lines is connected to a corresponding one of the plurality of semiconductor patterns;
• a plurality of first gate lines extending in the second horizontal direction, each of the plurality of first gate lines crosses a first region of a corresponding one of the plurality of semiconductor patterns;
• and
• a plurality of second gate lines extending in the second horizontal direction, each of the plurality of the second gate lines crosses a second region of a corresponding one of the plurality of semiconductor patterns.