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US 12,191,135 B2Granted
Two transistor gain cell memory with indium gallium zinc oxide
AssigneeIntel Corporation
InventorShigeki Tomishima
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Abstract
An example two transistor (2T) gain cell memory with indium-gallium-zinc-oxide (IGZO) transistors. Examples include IGZO transistors included in a dynamic random access memory (DRAM) cell. The IGZO transistors included in the DRAM cell are described as being formed or created in a back end (BE) metal process stack of an integrated circuit chip or die.
Claims8
A two-transistor dynamic random access memory (DRAM) cell comprising:
- a read bit line;
- a write bit line;
- a read word line;
- a write word line;
- a first indium-gallium-zinc-oxide (IGZO) transistor with a first gate region coupled to the write word line, a first controlled node region coupled to the write bit line, and a second controlled node region;
- and
- a second IGZO transistor with a second gate region, a third controlled node region coupled to the read word line, and a fourth controlled node region coupled to the read bit line, the second gate region of the second IGZO transistor coupled to the second controlled node region of the first IGZO transistor,
- wherein the first IGZO transistor is included in a first layer created in a back end (BE) metal process stack of an integrated circuit chip and the second IGZO transistor is included in a second layer created in the BE metal process stack.
5 more elements
A system comprising:
- an integrated circuit chip;
- and
- a two-transistor dynamic random access memory (DRAM) cell that includes:
- a first indium-gallium-zinc-oxide (IGZO) transistor with a first gate region coupled to a write word line, a first controlled node region coupled to a write bit line, and a second controlled node region;
- and
- a second IGZO transistor with a second gate region, a third controlled node region coupled to a read word line, and a fourth controlled node region coupled to a read bit line, the second gate region of the second IGZO transistor coupled to the second controlled node region of the first IGZO transistor,
- wherein the first IGZO transistor is included in a first layer created in a back end (BE) metal process stack of the integrated circuit chip and the second IGZO transistor is included in a second layer created in the BE metal process stack.
4 more elements
Dependencies are inferred from the claim text.