Semiconductor reaction chamber and atomic layer plasma etching apparatus

An atomic layer plasma etching apparatus comprising:

• a semiconductor reaction chamber including:
• a reaction chamber body;
• a dielectric window arranged above the reaction chamber body, a plasma generation area being located below the dielectric window;
• a spray head arranged between the dielectric window and a top wall of the reaction chamber body and dividing the plasma generation area into an strong plasma area at an upper part and a weak plasma area at a lower part, the spray head being arranged at the dielectric window to introduce plasma generating gas into the strong plasma area, a plurality of through-holes being distributed in a central area of the spray head and configured to allow a plasma in the strong plasma area to pass through, an edge area of the spray head being provided with a first gas channel, and a gas outlet end of the first gas channel being communicated with the weak plasma area;
• and
• a process reaction gas inlet member located on a side where a gas inlet end of the first gas channel of the spray head is located, a second gas channel being arranged in the process reaction gas inlet member, and the second gas channel being configured to introduce a process reaction gas into the weak plasma area;
• wherein the process reaction gas is different from the plasma generating gas;
• a base configured to carry a wafer and arranged in the semiconductor reaction chamber;
• and
• a center nozzle system arranged on the dielectric window and configured to introduce a plasma generation gas into the plasma generation area;
• an upper radio frequency system arranged above the dielectric window and configured to excite the plasma generation gas to form the plasma;
• and
• a lower radio frequency system electrically connected to the base and configured to load bias voltage power.