Single port memory with multiple memory operations per clock cycle

A memory circuitry device comprising:

• a block of memory comprising a memory bank coupled to a sense driver circuitry;
• a driver circuitry configured to generate a plurality of driver circuitry outputs;
• a selection circuitry configured to select one of the plurality of driver circuitry outputs based on a plurality of enable signals;
• a clock generation circuitry configured to receive the selected one of the plurality of driver circuitry outputs from the selection circuitry, and generate a clock signal based on at least the selected one of the plurality of driver circuitry outputs from the selection circuitry;
• and
• a self-time path circuitry of the memory configured to receive the clock signal and generate a reset signal based on the clock signal, wherein the plurality of driver circuitry outputs and the clock signal are based on the reset signal, and wherein the self-time path circuitry corresponds to one or more columns of the memory bank.

A method comprising:

• generating, by a driver circuitry, a plurality of driver circuitry outputs;
• selecting, by a selection circuitry, one of the plurality of driver circuitry outputs based on a plurality of enable signals;
• receiving, by a clock generation circuitry, the selected one of the plurality of driver circuitry outputs from the selection circuitry, and generating, by the clock generation circuitry, a clock signal based on at least the selected one of the plurality of driver circuitry outputs from the selection circuitry;
• and
• receiving, by a self-time path circuitry of a memory, the clock signal and generating a reset signal based on the clock signal, wherein the plurality of driver circuitry outputs and the clock signal are based on the reset signal, and wherein the self-time path circuitry corresponds to one or more columns of a memory bank.